Abstract
Electronic System Level refers to simulating a design at abstractions higher than RTL (register transfer level). Higher level means at transaction level where the low-level implementation detail is not of consequence, only the raw functionality and hardware-based concurrency. This chapter will discuss OSCI TLM2.0 standard definition, virtual platform examples, and how to use a virtual platform for design verification, among other topics.
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OVP. (n.d.). Open virtual platform. Retrieved from http://www.ovpworld.org
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Mehta, A.B. (2018). ESL (Electronic System Level) Verification Methodology. In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_11
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DOI: https://doi.org/10.1007/978-3-319-59418-7_11
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-59418-7
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