Abstract
In this chapter, implementation aspects of multi-rate systems are discussed. Two case studies, of which one is the a up-sampling filter for transmitter and the other is a down-sampling filter for receiver, are investigated.
The focus of the up-sampling filter is on the system-level arrangement. Design challenges on the system are analyzed and tackled. The systematic optimizations are first explored to minimize the design requirements on the DSP front end. From the implementation point of view, multiplier-less pulse-shaping filters with carry-save number applied to the entire signal-processing chain, as well as multiplier-less rotation and vectoring CORDICs (COordinate Rotation DIgital Computers) for rectangular-to-polar coordination conversions, is illustrated.
The down-sampling filter case focuses on the architecture selection of the multi-rate system. To be specific, fixed multiply additions and multiply–accumulator are discussed and compared. The carry-save number format is also exploited. The results show that a successful design trade-off requires careful combination of all the architectures, since each architecture has its advantages and drawbacks.
Keywords
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
S. Association and others. (2012). IEEE standard for information technology—telecommunications and information exchange between systems—local and metropolitan area networks—specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 3: Enhancements for very high throughput in the 60 GHz Band. IEEE, 1–628.
Khalaf, K., et al. (2016). Digitally modulated CMOS polar transmitters for highly-efficient mm-wave wireless communication. IEEE Journal of Solid-State Circuits, 99, 1–14.
Nariman, M., Shirinfar, F., Pamarti, S., Rofougaran, M., Rofougaran, R., & De Flaviis, F. (2013). A compact millimeter-wave energy transmission system for wireless applications. In Radio frequency integrated circuits symposium (RFIC), 2013 IEEE (pp. 407–410). Seattle, WA: IEEE. doi:10.1109/RFIC.2013.6569617.
Chan, W. L., & Long, J. R. (2010). A 60-GHz band 2 2 phased-array transmitter in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 45(12), 2682–2695.
Khalaf, K., Vidojkovic, V., Vaesen, K., Long, J. R., Van Thillo, W., & Wambacq, P. (2014). A digitally modulated 60GHz polar transmitter in 40nm CMOS. In 2014 IEEE. Radio Frequency Integrated Circuits Symposium (pp. 159–162). Tampa, FL: IEEE. doi:10.1109/RFIC.2014.6851685.
Vidojkovic, V., et al. (2013). A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication. In International solid-state circuits conference digest of technical papers, 2013 IEEE (pp. 236–237). San Francisco, CA: IEEE. doi:10.1109/ISSCC.2013.6487715.
Li, C., et al. (2016). Energy-efficient digital front-end processor for 60 GHz polar transmitter. Journal of Signal Processing Systems, 1939(8115), 1–13.
Volder, J. E. (1959). The CORDIC trigonometric computing technique. Electronic Computers IRE Transactions, 3, 330–334.
Li, C., et al. (2015). <30 mW rectangular-to-polar conversion processor in 802.11ad polar transmitter. In 2015 I.E. international conference on acoustics, speech and signal processing (ICASSP) (pp. 1022–1026). Piscataway: IEEE.
Li, C., et al. (2015). Opportunities and challenges of digital signal processing in deeply technology-scaled transceivers. Journal of Signal Processing Systems, 78(1), 5–19.
Losada, R. A., & Lyons, R. (2006). Reducing CIC filter complexity. IEEE Signal Processing Magazine, 23(4), 124–126.
Aboushady, H., Dumonteix, Y., Louërat, M.-M., & Mehrez, H. (2000). Efficient polyphase decomposition of comb decimation filters in sigma delta analog-to-digital converters. Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, 2000, 1, 432–435.
Hentschke, S., Herrfeld, A., Reifschneider, N,. Forster, D,. Heinemann, M., & Wicke, A. (1994). A flexible repetitive CSD code filter processor unit in CMOS. in ASIC conference and exhibit, 1994. Proceedings seventh annual IEEE international ASIC conference and exhibit, Rochester, NY, (pp. 261–264). doi: 10.1109/ASIC.1994.404562.
Noll, T. (1990). Carry-save arithmetic for high-speed digital signal processing. In 1990 IEEE international symposium on circuits and systems (pp. 982–986). New Orleans: IEEE. doi:10.1109/ISCAS.1990.112267.
Koc, C. K., & Hung, C. Y. (1990). Multi-operand modulo addition using carry save adders. Electronics Letters, 26(6), 361–363.
Gustafsson, O., Dempster, A. G., & Wanhammar, L. (2004). Multiplier blocks using carry-save adders. Circuits and Systems, 2004. ISCAS ‘04. Proceedings of the 2004 International Symposium on, 2004, 2, I-473–I-476.
Huang, Y., Kapoor, A., Rutten, R., & Pineda de Gyvez, J. (2015). A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with carry-save format numbers. Microprocessors and Microsystems, 39(8), 869–878.
Huang, Y., Kapoor, A., Rutten, R., & Pineda de Gyvez, J. (2013). A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers (pp. 1–4). Vilnius: 2013 NORCHIP. doi:10.1109/NORCHIP.2013.6702042.
Dadda, L. (1965). Some schemes for parallel multipliers. Alta Frequency, 34, 349–356.
Oklobdzija, V. G., Villeger, D., & Liu, S. S. (1996). A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers, 45(3), 294–306.
Huang, Y., Li, M., Li, C., Debacker, P., & Van der Perre, L. (2014). Computation-skip error resilient scheme for recursive CORDIC. In 2014 IEEE workshop on signal processing systems (SiPS) (pp. 1–6). Belfast: IEEE. doi:10.1109/SiPS.2014.6986061.
Bi, Z., & Dai, Y. (2012). Full custom data path of 16-bit CORDIC. In 2012 IEEE fifth international conference on advanced computational intelligence (ICACI) (pp. 993–998). Nanjing: IEEE. doi:10.1109/ICACI.2012.6463320.
Kwak, J. H., Piuri, V., & Swartzlander, E. E. (2000). Fault-tolerant high-performance CORDIC processors. In Proceedings IEEE international symposium on defect and fault tolerance in VLSI systems (pp. 164–172). Yamanashi: IEEE. doi:10.1109/DFTVS.2000.887154.
Umemoto, Y., et al. (2014). 28 nm 50% power-reducing contacted mask read only memory macro with 0.72-ns read access time using 2T pair bit cell and dynamic column source bias control technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(3), 575–584.
Lee, B., & Burgess, N. (2003). Some results on Taylor-series function approximation on FPGA. Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on, 2003, 2, 2198–2202.
Huang, Y., et al. (2016). A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter. In 2016 IEEE Asian solid-state circuits conference (A-SSCC) (pp. 333–336). Toyama: IEEE. doi:10.1109/ASSCC.2016.7844203.
Vaidyanathan, P. P. (1990). Multirate digital filters, filter banks, polyphase networks, and applications: A tutorial. Proceedings of the IEEE, 78(1), 56–93.
Coffey, M. W. (2003). Optimizing multistage decimation and interpolation processing. IEEE Signal Processing Letters, 10(4), 107–110.
van den Enden, A. W. M. (2001). Efficiency in multirate and complex digital signal processing. Amerongen: Delta Press.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Huang, Y., Li, C. (2018). Implementation Studies of Multi-rate Systems. In: Dolecek, G. (eds) Advances in Multirate Systems . Springer, Cham. https://doi.org/10.1007/978-3-319-59274-9_1
Download citation
DOI: https://doi.org/10.1007/978-3-319-59274-9_1
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-59273-2
Online ISBN: 978-3-319-59274-9
eBook Packages: EngineeringEngineering (R0)