Abstract
Faults modelling is essential to anticipate failures in critical systems. Traditionally, Static Fault Trees (SFTs) are employed to this end, but Temporal and Dynamic Fault Trees (TFTs and DFTs) are gaining evidence due to their enriched power to model and detect intricate propagation of faults that lead to a failure. SFTs structure can be abstracted to Boolean expressions. An algebra with an operator to express order is needed to abstract TFT and DFT structures. These expressions for SFT, TFT, and DFT are called structure expressions.
Architectural modelling languages, such as Architecture and Analysis Design Language (AADL), have been used to model components and systems relations, including modelling of faults, errors, failures, and fault propagation. AADL tools can perform Static Fault Tree Analysis, for the faults modelled using AADL’s Error Model Annex.
In previous work, we showed an Algebra of Temporal Faults to analyse the order of occurrence of faults extending Boolean algebra to perform analysis for Temporal and Dynamic fault trees. In this work, we show a parametrized logic to express nominal and erroneous behaviours, including faults modelling, provided an algebra and a set of operational modes. We show how to use this logic together with the Algebra of Temporal Faults to analyse the occurrence of faults as well as their order and propagation. The logic created in this work is intended to help analysts to consider all possible situations in complex expressions with order-related operators, avoiding to miss some subtle (but relevant) combination.
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Notes
- 1.
Whether a top event indeed causes a catastrophic or major failure is out of the scope of this paper; we consider that, if it is possible that such failure occurs, then it will.
- 2.
Pandora stands for: P-AND-ORA, which translates to Priority AND, Time.
References
SAE ARP4761 Guidelines and Methods for Conducting the Safety Assessment Process on Civil Airborne Systems and Equipment, December 1996
SAE Architecture Analysis and Design Language (AADL) Annex Volume 1: Annex A: ARINC653 Annex, Annex C: Code Generation Annex, Annex E: Error Model Annex. Technical report, SAE International (2015)
Akers, S.B.: Binary decision diagrams. IEEE Trans. Comput. C–27(6), 509–516 (1978)
ANAC. Aeronautical Product Certification. DOU No. 230, Seção 1, p. 28, 01 December 2011, (2011)
Andrews, J.D.: The use of not logic in fault tree analysis. Qual. Reliab. Eng. Int. 17(3), 143–150 (2001)
Boute, R.T.: The binary decision machine as programmable controller. Euromicro Newslett. 2(1), 16–22 (1976)
Didier, A.L.R., Mota, A.: Identifying hardware failures systematically. In: Gheyi, R., Naumann, D. (eds.) Formal Methods: Foundations and Applications. Lecture Notes in Computer Science, vol. 7498, pp. 115–130. Springer, Heidelberg (2012)
Didier, A.L.R., Mota, A.: An algebra of temporal faults. Inf. Syst. Front. 18, 967–980 (2016)
Dugan, J.B., Bavuso, S.J., Boyd, M.A.: Dynamic fault-tree models for fault-tolerant computer systems. IEEE Trans. Reliab. 41(3), 363–377 (1992)
FAA. RTCA, Inc., Document RTCA/DO-178B. U.S. Dept. of Transportation, Federal Aviation Administration, Washington, D.C. (1993)
FAA. Part 25 - Airworthiness Standards: Transport Category Airplanes. report, Federal Aviation Administration (FAA), USA (2007)
Feiler, P.H., Gluch, D.P., Hudak, J.J.: The Architecture Analysis & Design Language (AADL): An Introduction. CMU/SEI–2006–TN–011, February 2006
Givant, S., Halmos, P.: Introduction to Boolean Algebras. Undergraduate Texts in Mathematics, vol. XIV. Springer, New York (2009)
Hoare, C.A.R., He, J.: Unifying Theories of Programming, vol. 14. Prentice Hall, Englewood Cliffs (1998)
Koren, I., Krishna, C.M.: Fault Tolerant Systems. Morgan Kaufmann Publishers Inc., San Francisco (2007)
Merle, G.: Algebraic modelling of Dynamic Fault Trees, contribution to qualitative and quantitative analysis. Theses, École normale supérieure de Cachan - ENS Cachan (2010)
Merle, G., Roussel, J.-M., Lesage, J.-J.: Algebraic determination of the structure function of Dynamic Fault Trees. Reliab. Eng. Syst. Saf. 96(2), 267–277 (2011)
Merle, G., Roussel, J.-M., Lesage, J.-J.: Dynamic fault tree analysis based on the structure function. In: 2011 Proceedings - Annual Reliability and Maintainability Symposium, January 2011
Merle, G., Roussel, J.-M., Lesage, J.-J.: Quantitative analysis of dynamic fault trees based on the structure function. Qual. Reliab. Eng. Int. 30(1), 143–156 (2014)
Merle, G., Roussel, J.-M., Lesage, J.-J., Bobbio, A.: Probabilistic algebraic analysis of fault trees with priority dynamic gates and repeated events. IEEE Trans. Reliab. 59(1), 250–261 (2010)
O’Connor, P.D.T., Newton, D., Bromley, R.: Practical Reliability Engineering. Wiley, Hoboken (2002)
Oliva, S.: Non-coherent fault trees can be misleading. e-J. Syst. Saf. 42(3), 1–5 (2006)
Tannous, O., Xing, L., Dugan, J.B.: Reliability analysis of warm standby systems using sequential BDD. In: 2011 Proceedings - Annual Reliability and Maintainability Symposium, January 2011
Vesely, W., Goldberg, F.F., Roberts, N.H., Haasl, D.F.: Fault Tree Handbook. Number NUREG-0492. US Independent Agencies and Commissions (1981)
Walker, M.D.: Pandora: a logic for the qualitative analysis of temporal fault trees. Ph.D. thesis, University of Hull (2009)
Walker, M.D., Papadopoulos, Y.: Synthesis and analysis of temporal fault trees with PANDORA: the time of Priority AND gates. Nonlinear Anal. Hybrid Syst. 2(2), 368–382 (2008)
Walker, M.D., Papadopoulos, Y.: Qualitative temporal analysis: towards a full implementation of the fault tree handbook. Control Eng. Pract. 17(10), 1115–1125 (2009)
Walker, M.D., Papadopoulos, Y.: A hierarchical method for the reduction of temporal expressions in Pandora. In: Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems, DYADEM-FTS 2010, pp. 7–12. ACM, New York (2010)
Xing, L., Tannous, O., Dugan, J.B.: Reliability analysis of nonrepairable cold-standby systems using sequential binary decision diagrams. IEEE Trans. Syst. Man Cybern. A 42(3), 715–726 (2012)
Acknowledgements
We would like to thank Alexander Romanovsky, Zoe Andrews and Richard Payne for all discussions about fault modelling and dependability. This work was funded by CNPq, grants 476821/2011-8, 442859/2014-7, and 246956/2012-7, and by FACEPE grant IBPG-0408-1.03/11. This work was partially supported by the National Institute of Science and Technology for Software Engineering (INES, http://www.ines.org.br), funded by CNPq and FACEPE, grants 573964/2008-4 and APQ-1037-1.03/08.
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Didier, A., Mota, A. (2018). Reasoning About Temporal Faults Using an Activation Logic. In: Rubin, S., Bouabana-Tebibel, T. (eds) Quality Software Through Reuse and Integration. FMI IRI 2016 2016 2016. Advances in Intelligent Systems and Computing, vol 561. Springer, Cham. https://doi.org/10.1007/978-3-319-56157-8_13
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