Abstract
Specification, hardware platforms and system software provide us with the basic ingredients which we need for designing embedded systems. During the design process, we must validate and evaluate designs rather frequently. Therefore, we will describe validation and evaluation before we talk about design steps. Validation and evaluation, even though different from each other, are very much linked.
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Notes
- 1.
We assume that students are familiar with concepts of caches.
- 2.
Unfortunately, this strategy is typically not available for processors.
- 3.
Our presentation of the real-time calculus is based on Thiele’s presentation in the book edited by Zurawski [513]. Resulting considerations at the system level have been called modular performance analysis (MPA).
- 4.
We leave out the subtle discussion of dis-continuities at \(\Delta =n*T\).
- 5.
Images are included with permission of David Atienza (EPFL). Images were obtained as part of the cooperation between EPFL and ST Microelectronics in the FP7 EU Project titled: “PRO3D: Programming for Future 3D Architectures with Many Cores”.
- 6.
This result motivates denoting the failure rate and the constant of the exponential distribution with the same symbol.
- 7.
Therefore, the so-called log-normal distribution is sometimes considered.
- 8.
Consistent with the ANSI/IEEE standard 91, we use the symbols &, =1 and \(\ge \) 1 to denote and-, xor-, and or-gates, respectively.
- 9.
This initial text on formal verification was based on a guest lecture given by Tiziana Margaria at TU Dortmund.
- 10.
See http://www.uppaal.org for the academic and http://www.uppaal.com for the commercial version.
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Marwedel, P. (2018). Evaluation and Validation. In: Embedded System Design. Embedded Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-56045-8_5
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DOI: https://doi.org/10.1007/978-3-319-56045-8_5
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