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Issues on GPU Parallel Implementation of Evolutionary High-Dimensional Multi-objective Feature Selection

  • Juan José Escobar
  • Julio Ortega
  • Jesús González
  • Miguel Damas
  • Beatriz Prieto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10199)

Abstract

The interest on applications that analyse large volumes of high dimensional data has grown recently. Many of these applications related to the so-called Big Data show different implicit parallelism that can benefit from the efficient use, in terms of performance and power consumption, of Graphics Processing Unit (GPU) accelerators. Although the GPU microarchitectures make possible the acceleration of applications by exploiting parallelism at different levels, the characteristics of their memory hierarchy and the location of GPUs as coprocessors require a careful organization of the memory access patterns and data transferences to get efficient speedups. This paper aims to take advantage of heterogeneous parallel codes on GPUs to accelerate evolutionary approaches in Electroencephalogram (EEG) classification and feature selection in the context of Brain Computer Interface (BCI) tasks. The results show the benefits of taking into account not only the data parallelism achievable by GPUs, but also the memory access patterns, in order to increase the speedups achieved by superscalar cores.

Keywords

EEG classification Feature selection GPU Heterogeneous parallel architectures Multi-objective optimization OpenCL 

Notes

Acknowledgements

This work has been funded by project TIN2015-67020-P (Spanish “Ministerio de Economá y Competitividad” and FEDER funds). We also thank the BCI laboratory of the University of Essex, and especially prof. John Q. Gan, for allowing us to use their databases.

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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Juan José Escobar
    • 1
  • Julio Ortega
    • 1
  • Jesús González
    • 1
  • Miguel Damas
    • 1
  • Beatriz Prieto
    • 1
  1. 1.Department of Computer Architecture and Technology, CITICUniversity of GranadaGranadaSpain

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