Abstract
The design of fractional-order capacitors and inductor emulators is introduced in a systematic way procedure, where the second-order approximation of the CFE is utilized in order to approximate the variable s α of fractional calculus. OTAs are employed as building blocks, using MOS transistors biased in subthreshold region, offering the advantage of operating in a low voltage environment. The emulation schemes that have been proposed are voltage excited, as well as current excited in order to be available for different types of applications based on potentiostatic and galvanostatic measurements, respectively. Both emulators (capacitor and inductor) are fabricated in AMS 0.35 μm CMOS technology, the efficiency of which is verified through experimental results. As a design example, a fractional-order resonator is presented.
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Tsirimokou, G., Psychalinos, C., Elwakil, A. (2017). Emulation of Fractional-Order Capacitors (CPEs) and Inductors (FOIs). In: Design of CMOS Analog Integrated Fractional-Order Circuits. SpringerBriefs in Electrical and Computer Engineering. Springer, Cham. https://doi.org/10.1007/978-3-319-55633-8_5
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DOI: https://doi.org/10.1007/978-3-319-55633-8_5
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