Advertisement

SONOS Split-Gate eFlash Memory

  • Takashi ItoEmail author
  • Yasuhiko Taito
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Technological details about SONOS split-gate eFlash memory are described. First, memory cell structure, basic cell-operation principles and eFlash-fabrication process are introduced. Subsequently, basic array architecture and read/program/erase operations are explained by block/schematic diagrams of corresponding peripheral circuits. A data-retention model of the SONOS split-gate eFlash memory is also discussed. Finally, advanced-circuit and process technologies are described. As for circuit technologies, the techniques to expand the application range especially for automotive use, which requires both high performance and high reliability are described. Regarding process technology, the scalability of SONOS split-gate eFlash memory is explained placing emphasis on the measurement data for affinity with advanced-logic CMOS process.

References

  1. 1.
    Y. Kawashima, T. Hashimoto, I. Yamakawa, Investigation of the data retention mechanism and modeling for the high reliability embedded split-gate MONOS flash memory. IEEE International Reliability Physics Symposium, pp. MY.6.1–MY.6.5 (2015)Google Scholar
  2. 2.
    Y. Taito, M. Nakano, H. Okimoto, D. Okada, T. Ito, T. Kono, K. Noguchi, H. Hidaka, T. Yamauchi, A 28 nm embedded SG-MONOS flash macro for automotive achieving 200 MHz read operation and 2.0 MB/s write throughput at Tj of 170°C. ISSCC digest of technical papers, pp. 132–133 (2015)Google Scholar
  3. 3.
    Y. Taito, T. Kono, M. Nakano, T. Saito, T. Ito, K. Noguchi, H. Hidaka, T. Yamauchi, A 28 nm embedded split-gate MONOS (SG-MONOS) flash macro for automotive achieving 6.4 GB/s read throughput by 200 MHz no-wait read operation and 2.0 MB/s write throughput at Tj of 170°C. IEEE J. Solid-State Circuits 51(1), 213–221 (2016)CrossRefGoogle Scholar
  4. 4.
    M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, G. Cohen, Data retention reliability model of NROM nonvolatile memory products. IEEE Trans. Device Mater. Reliab. 4, 404–415 (2004)CrossRefGoogle Scholar
  5. 5.
    P.B. Kumar, E. Murakami, S. Kamohara, S. Mahapatra, Endurance and retention characteristics of SONOS EEPROMs operated using BTBT induced hot hole erase. in Proceedings IRPS, pp. 699–700 (2006)Google Scholar
  6. 6.
    T. Kono, T. Ito, T. Tsuruda, T. Nishiyama, T. Nagasawa, T. Ogawa, Y. Kawashima, H. Hidaka, T. Yamauchi, 40 nm embedded SG-MONOS flash macros for automotive with 160 MHz random access for code and endurance over 10 M cycles for data. ISSCC digest of technical papers, pp. 212–214 (2013)Google Scholar
  7. 7.
    T. Kono, T. Ito, T. Tsuruda, T. Nishiyama, T. Nagasawa, T. Ogawa, Y. Kawashima, H. Hidaka, T. Yamauchi, 40-nm embedded split-gate MONOS (SG-MONOS) flash macros for automotive with 160-MHz random access for code and endurance over 10 M cycles for data at the junction temperature of 170°C. IEEE J. Solid-State Circuits 49(1), 154–166 (2014)CrossRefGoogle Scholar
  8. 8.
    L.Q. Luo, Y.T. Chow, X.S. Cai, F. Zhang, Z.Q. Teo, D.X. Wang, K.Y. Lim, B.B. Zhou, J.Q. Liu, A. Yeo, T.L. Chang, Y.J. Kong, C.W. Yap, S. Lup, R. Long, J.B. Tan, D. Shum, N. Do, J.H. Kim, P. Ghazavi, V. Tiwari, Functionality demonstration of a high-density 1.1 V self-aligned split-gate NVM cell embedded into LP 40 nm CMOS for automotive and smart card applications. IEEE International Memory Workshop, pp. 165–168 (2015)Google Scholar
  9. 9.
    S. Tsuda, Y. Kawashima, K. Sonoda, A. Yoshitomi, T. Mihara, S. Narumi, M. Inoue, S. Muranaka, T. Maruyama, T. Yamashita, Y. Yamaguchi, D. Hisamoto, First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14 nm-node and beyond. IEDM digest of technical papers, pp. 11.1.1–11.1.4 (2016)Google Scholar

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  1. 1.Core Technology Business DivisionRenesas ElectronicsKodaira-shiJapan

Personalised recommendations