Abstract
Technological details about SONOS split-gate eFlash memory are described. First, memory cell structure, basic cell-operation principles and eFlash-fabrication process are introduced. Subsequently, basic array architecture and read/program/erase operations are explained by block/schematic diagrams of corresponding peripheral circuits. A data-retention model of the SONOS split-gate eFlash memory is also discussed. Finally, advanced-circuit and process technologies are described. As for circuit technologies, the techniques to expand the application range especially for automotive use, which requires both high performance and high reliability are described. Regarding process technology, the scalability of SONOS split-gate eFlash memory is explained placing emphasis on the measurement data for affinity with advanced-logic CMOS process.
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Ito, T., Taito, Y. (2018). SONOS Split-Gate eFlash Memory. In: Hidaka, H. (eds) Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-55306-1_7
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DOI: https://doi.org/10.1007/978-3-319-55306-1_7
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