Abstract
The Reduced Complexity Many-Core architecture (RC/MC) targets to simplify timing analysis by increasing the predictability of all components. Since shared memory interference is a major source of pessimism in many-core systems, fine-grained message passing between small cores with private memories is used instead of a global shared memory.
In this paper, the RC/MC architecture is presented and evaluated by three models: a VHDL model that can be used to synthesise prototypes with up to \(6\times 6\) cores on an FPGA; a simulation model written in C that can be used for cycle-accurate simulation of more than 4096 cores; and a timing model for static timing analysis.
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Notes
- 1.
Altera uses the term Adaptive Logic Module (ALM) for their elementary logic block, basically a lookup table with 6 inputs and 2 outputs (6-LUT). One ALM is equivalent to approximately 2.5 lookup tables with 4 inputs and 1 output (4-LUT).
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Mische, J., Frieb, M., Stegmeier, A., Ungerer, T. (2017). Reduced Complexity Many-Core: Timing Predictability Due to Message-Passing. In: Knoop, J., Karl, W., Schulz, M., Inoue, K., Pionteck, T. (eds) Architecture of Computing Systems - ARCS 2017. ARCS 2017. Lecture Notes in Computer Science(), vol 10172. Springer, Cham. https://doi.org/10.1007/978-3-319-54999-6_11
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