Skip to main content

New Solutions for Cross-Layer System-Level and High-Level Synthesis

  • Chapter
  • First Online:
Emerging Technology and Architecture for Big-data Analytics
  • 1584 Accesses

Abstract

The rise of the Internet of Things—billions of internet connected sensors constantly monitoring the physical environment has coincided with the rise of big data and advanced data analytics that can effectively gather, analyze, generate insights about the data, and perform decision making. Data analytics allows analysis and optimization of massive datasets: deep analysis has led to advancements in business operations optimization, natural language processing, computer vision applications such as object classification, etc. Furthermore, data-processing platforms such as Apache Hadoop (White, Hadoop: the definitive guide. O’Reilly Media, Sebastopol, 2009) have become primary datacenter applications, but the rise of massive data processing also has a major impact on the increasing demand for both datacenter computation and data processing in edge devices to improve scalability of massive sensing applications.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    AutoPilot was acquired by Xilinx, and is now Vivado HLS.

  2. 2.

    A basic block is a portion of the code within a program with only one entry point, only one exit point and without conditional branches.

References

  1. J.R. Allen, K. Kennedy, C. Porterfield, J. Warren, Conversion of control dependence to data dependence, in Proceedings of the 10th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages (ACM, Austin, 1983), pp. 177–189

    Google Scholar 

  2. Altera Inc., Quartus II Software, http://www.altera.com/products/software/

  3. Altera Inc., Quartus II Handbook (2013). https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/archives/quartusii_handbook_archive_131.pdf

    Google Scholar 

  4. P. Ashar, S. Dey, S. Malik, Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. 14 (9), 1067–1075 (1995)

    Google Scholar 

  5. C. Bastoul, Code generation in the polyhedral model is easier than you think, in Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, PACT ’04 (IEEE Computer Society, Washington, DC, 2004), pp. 7–16

    Google Scholar 

  6. U. Bondhugula, A. Hartono, J. Ramanujam, P. Sadayappan, A practical automatic polyhedral parallelizer and locality optimizer, in PLDI (2008), pp. 101–113

    Google Scholar 

  7. Y. Chen, S.T. Gurumani, Y. Liang, G. Li, D. Guo, K. Rupnow, D. Chen, Fcuda-noc: a scalable and efficient network-on-chip implementation for the cuda-to-fpga flow. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24 (6), 2220–2233 (2016)

    Google Scholar 

  8. Y. Chen, T. Nguyen, Y. Chen, S. Gurumani, Y. Liang, K. Rupnow, J. Cong, W.M. Hwu, D. Chen, FCUDA-bus: hierarchical and scalable bus architecture generation on FPGAs with high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. PP (99), 1–1 (2016)

    Google Scholar 

  9. L. Cheng, D. Chen, M.D. Wong, M. Hutton, J. Govig, Timing constraint-driven technology mapping for fpgas considering false paths and multi-clock domains, in ICCAD (2007), pp. 370–375

    Google Scholar 

  10. F. Computing, Falcon computing solutions, http://www.falcon-computing.com

  11. J. Cong, Z. Zhang, An efficient and versatile scheduling algorithm based on sdc formulation, in DAC (2006), pp. 433–438

    Google Scholar 

  12. R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, F.K. Zadeck, Efficiently computing static single assignment form and the control dependence graph. ACM Trans. Program. Lang. Syst. 13 (4), 451–490 (1991)

    Google Scholar 

  13. V. D’silva, D. Kroening, Fixed points for multi-cycle path detection, in DATE (2009), pp. 1710–1715

    Google Scholar 

  14. D.D. Gajski, N.D. Dutt, A.C.-H. Wu, S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design (Kluwer Academic, Norwell, MA, 1992)

    Google Scholar 

  15. Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii, Chstone: a benchmark program suite for practical c-based high-level synthesis, in ISCAS (2008), pp. 1192–1195

    Google Scholar 

  16. H. Higuchi, Y. Matsunaga, Enhancing the performance of multi-cycle path analysis in an industrial setting, in ASP-DAC (2004), pp. 192–197

    Google Scholar 

  17. M. Lam, Software pipelining: an effective scheduling technique for vliw machines, in Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation, PLDI ’88 (ACM, New York, NY, 1988), pp. 318–328

    Google Scholar 

  18. V. Manohararajah, G.R. Chiu, D.P. Singh, S.D. Brown, Predicting interconnect delay for physical synthesis in a fpga cad flow. IEEE Trans. Very Large Scale Integr. 15 (8), 895–903 (2007)

    Google Scholar 

  19. K. Nakamura, K. Takagi, S. Kimura, K. Watanabe, Waiting false path analysis of sequential logic circuits for performance optimization, in ICCAD (1998), pp. 392–395

    Google Scholar 

  20. T. Nguyen, S. Gurumani, K. Rupnow, D. Chen, Fcuda-soc: platform integration for field-programmable soc with the cuda-to-fpga compiler, in Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA ’16 (ACM, New York, NY, 2016), pp. 5–14

    Google Scholar 

  21. J.C. Park, M. Schlansker, On predicated execution. Technical report, Technical Report HPL-91-58, HP Labs (1991)

    Google Scholar 

  22. Pocc, The polyhedral compiler collection, http://www.cse.ohio-state.edu/~pouchet/software/pocc/

  23. Polyhedral benchmark suite v3.1, http://www.cse.ohio-state.edu/~pouchet/software/poly_bench/

  24. A. Putnam, A. Caulfield, E. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, E. Peterson, A. Smith, J. Thong, P.Y. Xiao, D. Burger, J. Larus, G.P. Gopal, S. Pope, A reconfigurable fabric for accelerating large-scale datacenter services, in 41st Annual International Symposium on Computer Architecture (ISCA) (2014)

    Google Scholar 

  25. R. Ranjan, V. Singhal, F. Somenzi, R. Brayton, On the optimization power of retiming and resynthesis transformations, in ICCAD (1998), pp. 402–407

    Google Scholar 

  26. A. Saldanha, H. Harkness, P. McGeer, R. Brayton, A. Sangiovanni-Vincentelli, Performance optimization using exact sensitization, in DAC (1994), pp. 425–429

    Google Scholar 

  27. The Cloog code generator, http://www.cloog.org

  28. R.A. Towle, Control and data dependence for program transformations. PhD thesis, University of Illinois at Urbana-Champaign (1976)

    Google Scholar 

  29. T. White, Hadoop: The Definitive Guide, 1st edn. (O’Reilly Media, Sebastopol, 2009)

    Google Scholar 

  30. Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, J. Cong, Autopilot: a platform-based esl synthesis system, in High-Level Synthesis: From Algorithm to Digital Circuit (Springer, Dordrecht, 2008), pp. 99–112

    Google Scholar 

  31. H. Zheng, S. Gurumani, L. Yang, D. Chen, K. Rupnow, High-level synthesis with behavioral level multi-cycle path analysis, in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL) (2013), pp. 1–8

    Google Scholar 

  32. H. Zheng, S.T. Gurumani, K. Rupnow, D. Chen, Fast and effective placement and routing directed high-level synthesis for FPGAs, in Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ACM, New York, 2014), pp. 1–10

    Google Scholar 

  33. H. Zheng, S.T. Gurumani, L. Yang, D. Chen, K. Rupnow, High-level synthesis with behavioral-level multicycle path analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12), 1832–1845 (2014)

    Google Scholar 

  34. W. Zuo, P. Li, D. Chen, L.-N. Pouchet, S. Zhong, J. Cong, Improving polyhedral code generation for high-level synthesis, in 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2013), pp. 1–10

    Google Scholar 

  35. W. Zuo, Y. Liang, P. Li, K. Rupnow, D. Chen, J. Cong, Improving high level synthesis optimization opportunity through polyhedral transformations, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA ’13 (ACM, New York, NY, 2013), pp. 9–18

    Google Scholar 

Download references

Acknowledgements

This work was supported in part by the CFAR Center, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by A*STAR under the Human-Centered Cyber-Physical Systems (HCCS) grant.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Deming Chen .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this chapter

Cite this chapter

Zuo, W., Gurumani, S., Rupnow, K., Chen, D. (2017). New Solutions for Cross-Layer System-Level and High-Level Synthesis. In: Chattopadhyay, A., Chang, C., Yu, H. (eds) Emerging Technology and Architecture for Big-data Analytics. Springer, Cham. https://doi.org/10.1007/978-3-319-54840-1_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-54840-1_5

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-54839-5

  • Online ISBN: 978-3-319-54840-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics