Abstract
Energy efficiency has emerged as a major barrier to system performance and scalability, especially when dealing with applications which require processing large datasets. These data-intensive kernels differentiate themselves from compute-intensive kernels in that increased processor performance through parallel execution and technology scaling are unlikely to sufficiently improve energy-efficiency. This chapter describes two embodiments of a novel and reconfigurable memory-based computing architecture which is designed to handle data-intensive kernels in a scalable and energy-efficient manner, suitable for next-generation systems.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
C. Babecki, W. Qian, S. Paul, R. Karam, S. Bhunia, An embedded memory-centric reconfigurable hardware accelerator for security applications. IEEE Trans. Comput. (99):1–1 (2016). doi:10.1109/TC.2015.2512858
M. Bohr, A 30 year retrospective on dennard’s mosfet scaling paper. IEEE Solid-State Circuits Soc. Newsl. 12 (1), 11–13 (2007)
H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in 2011 38th Annual International Symposium on Computer Architecture (ISCA) (IEEE, New York, 2011), pp. 365–376
Intl Solid State Circuits Conference (2013) ISSCC 2013 Tech Trends. http://isscc.org/trends
R. Karam, R. Puri, S. Ghosh, S. Bhunia, Emerging trends in design and applications of memory-based computing and content-addressable memories. Proc. IEEE 103 (8), 1311–1330 (2015). doi:10.1109/JPROC.2015.2434888
R. Karam, K. Yang, S. Bhunia, Energy-efficient reconfigurable computing using spintronic memory, in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) (2015), pp. 1–4. doi:10.1109/MWSCAS.2015.7282213
R. Karam, R. Puri, S. Bhunia, Energy-efficient adaptive hardware accelerator for text mining application kernels. IEEE Trans. Very Large Scale Integr. 24, 3526–3537 (2016)
S. Paul, S. Chatterjee, S. Mukhopadhyay, S. Bhunia, Energy-efficient reconfigurable computing using a circuit-architecture-software co-design approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3), 369–380 (2011)
S. Paul, R. Karam, S. Bhunia, R. Puri, Energy-efficient hardware acceleration through computing in the memory, in 2014 Design, Automation Test in Europe Conference Exhibition (DATE) (2014). doi:10.7873/DATE.2014.279
S. Paul, A. Krishna, W. Qian, R. Karam, S. Bhunia, Maha: an energy-efficient malleable hardware accelerator for data-intensive applications. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23 (6), 1005–1016 (2015) doi:10.1109/TVLSI.2014.2332538
S. Pawlowski, Architectural considerations for todays technology trends (2013). http://eecs.oregonstate.edu/
W. Qian, P.Y. Chen, R. Karam, L. Gao, S. Bhunia, S. Yu, Energy-efficient adaptive computing with multifunctional memory. Trans. Circuits Systems (2016)
H. Wong, V. Betz, J. Rose, Comparing fpga vs. custom cmos and the impact on processor microarchitecture, in Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (ACM, New York, 2011), pp. 5–14
H.S.P. Wong, H.Y. Lee, S. Yu, Y.S. Chen, Y. Wu, P.S. Chen, B. Lee, F.T. Chen, M.J. Tsai, Metal–oxide rram. Proc. IEEE 100(6):1951–1970 (2012)
X. Wu, X. Chen, S. Hurst, Mapping of reed-muller coefficients and the minimisation of exclusive or-switching functions. IEE Proc. E-Comput. Digital Tech. 129 (1), 15–20 (1982)
Acknowledgements
Robert Karam, Somnath Paul, and Swarup Bhunia would like to acknowledge the contributions of Christopher Babecki (Intel), Pai-Yu Chen (Arizona State University), Dr. Ligang Gao (Arizona State University), Dr. Ruchir Puri (IBM T. J. Watson Research Lab), Dr. Wenchao Qian (Xilinx), and Dr. Shimeng Yu (Arizona State University).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
Karam, R., Paul, S., Bhunia, S. (2017). Compute-in-Memory Architecture for Data-Intensive Kernels. In: Chattopadhyay, A., Chang, C., Yu, H. (eds) Emerging Technology and Architecture for Big-data Analytics. Springer, Cham. https://doi.org/10.1007/978-3-319-54840-1_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-54840-1_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-54839-5
Online ISBN: 978-3-319-54840-1
eBook Packages: EngineeringEngineering (R0)