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Conclusions

  • Ran WangEmail author
  • Krishnendu Chakrabarty
Chapter
  • 317 Downloads

Abstract

The semiconductor industry continues to be faced with growing market demand for integrated circuits with increasing functionality and higher performance. However, continued scaling to meet these goals results in increased interconnect delay, which tends to be the key limiter for chip performance.

References

  1. 1.
    J. Rearick, Testing the AMD FIJI GPU in the 3rd Dimension, in Keynote Speech, ITC 3D Test Workshop (2015)Google Scholar
  2. 2.
    G. Van der Plas et al., Design issues and considerations for low-cost 3-D TSV IC technology. IEEE J. Solid State Circuits 46(1), 293–307 (2011)CrossRefGoogle Scholar
  3. 3.
    D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings of International Conference on Computer-Aided Design, 2009, pp. 674–680Google Scholar
  4. 4.
    A.W. Topol et al., Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs), in IEEE International Electron Devices Meeting (IEDM), 2005, pp. 352–355Google Scholar
  5. 5.
    C. Yu, C. Chang, H. Wang, J. Chang, L. Huang, C. Kuo, S. Tai, S. Hou, W. Lin, E. Liao, K. Yang, T. Wu, W. Chiou, C. Tung, S. Jeng, C. Yu, TSV process optimization for reduced device impact on 28nm CMOS, in IEEE Symposium on VLSI Technology, 2011, pp. 138–139Google Scholar
  6. 6.
    M. Vinet et al., Monolithic 3D integration: a powerful alternative to classical 2D scaling, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, pp. 1–3Google Scholar
  7. 7.
    P. Batude et al., Advances in 3D CMOS sequential integration, in IEEE International Electron Devices Meeting (IEDM), 2009, pp. 1–4Google Scholar
  8. 8.
    Z. Or-Bach, Z. Wurman, Method for design and manufacturing of a 3D semiconductor device, U.S. Patent 8,669,778 Mar 2014Google Scholar
  9. 9.
    P. Batude et al., Advances, challenges and opportunities in 3D CMOS sequential integration, in IEEE International Electron Devices Meeting (IEDM), 2011, pp. 151–154Google Scholar
  10. 10.
    P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, P.-E. Gaillardon, 3-D sequential integration: a key enabling technology for heterogeneous co-integration of new function with CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(4), 714–722 (2012)CrossRefGoogle Scholar
  11. 11.
    K. Arabi, 3D VLSI: a scalable integration beyond 2D, Keynote Speech ISPD (2015)Google Scholar
  12. 12.
    B. Noia, K. Chakrabarty, Design-for-test and test optimization techniques for TSV-based 3D stacked ICs, (Springer, Heidelberg, 2014)Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Nvidia (United States)SunnyvaleUSA
  2. 2.Department of ECEDuke UniversityDurhamUSA

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