A Programmable Method for Low-Power Scan Shift in SoC Dies

  • Ran WangEmail author
  • Krishnendu Chakrabarty


The increase in die size and the number of scan flip-flops has resulted in an overwhelming increase in the number of test patterns as well as the number of shift cycles per pattern for the dies in 2.5D ICs. This has in turn led to significantly increased switching activity. One potential solution is to apply a single input clock to the SoC and derive multiple test clocks inside each block [1].


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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Nvidia (United States)SunnyvaleUSA
  2. 2.Department of ECEDuke UniversityDurhamUSA

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