Abstract
A large number of input and output (I/O) ports are available for the dies in a 2.5D IC.
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- 1.
Those interconnects are tested in the previous test round and thus not considered in the current test round.
- 2.
Note that they cannot share all the input scan channels in order to avoid resulting in untested faults in the combinational logic.
- 3.
Details are not disclosed due to confidentiality reasons.
- 4.
Due to the confidentiality reasons, only A69 and A531 are released for our analysis in this chapter.
References
K. Kumagai, Y. Yoneda, H. Izumino, H. Shimojo, M. Sunohara, T. Kurihara, M. Higashi, Y. Mabuchi, A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect, in IEEE Electronic Components and Technology Conference, 2008, pp. 571–576
S.-Y. Huang, L.-R. Huang, Delay testing and characterization of post-bond interposer wires in 2.5-D ICs, in IEEE International Test Conference (2013)
S.-Y. Huang, J.-Y. Lee, K.-H. Tsai, W.-T. Cheng, At-speed BIST for interposer wires supporting on-the-spot diagnosis, in International On-Line Test Symposium (2013)
C.-C. Chi, B.-Y. Lin, C.-W. Wu, M.-J. Wang, H.-C. Lin, C.-N. Peng, On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs. IEEE Des. Test 31(4), 16–26 (2014)
C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base, in IEEE International Test Conference (2011)
S.K. Goel, S. Adham, M.-J. Wang, J.-J. Chen, T.-C. Huang, A. Mehta, F. Lee, V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, J. Cho, H. Lee, J. Choi, S. Kim, Test and debug strategy for TSMC CoWoSTM stacking process based heterogeneous 3D IC: a silicon case study, in IEEE International Test Conference (2013)
R. Wang, K. Chakrabarty, S. Bhawmik, Built-in self-test and test scheduling for interposer-based 2.5 D ICs. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 20(4), 58 (2015)
IEEE Std 1500TM-2005, IEEE standard testability method for embedded core-based integrated circuits, in IEEE Computer Society, IEEE, New York, NY, USA, Aug 2005
S. Mitra, K.S. Kim, XPAND: an efficient test stimulus compression technique. IEEE Trans. Comput. 55(2), 163–173 (2006)
C. Krishna, N.A. Touba, Adjustable width linear combinational scan vector decompression, in IEEE/ACM International Conference on Computer-Aided Design, 2003, p. 863
B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, D. Wheater, A smartBIST variant with guaranteed encoding, in IEEE Asian Test Symposium, 2001, pp. 325–330
C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, B. Koenemann, OPMISR: the foundation for compressed ATPG vectors, in IEEE International Test Conference, 2001, pp. 748–757
J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, Embedded deterministic test. IEEE Trans. Comput. Aided Des. Int. Circuits Syst. 23, 776–792 (2004)
P.T. Wagner, Interconnect testing with boundary scan, in IEEE International Test Conference, 1987, pp. 52–57
H. Fernau, J. Kneis, D. Kratsch, A. Langer, M. Liedloff, D. Raible, P. Rossmanith, An Exact Algorithm for the Maximum Leaf Spanning Tree Problem, in Parameterized and Exact Computation (Springer, Heidelberg, 2009), pp. 161–172
Mentor graphics testkompress, http://www.mentor.com/products/silicon-yield/products/testkompress (2013)
Xpress-MP, http://www.fico.com/en/Products/DMTools/xpress-overview/Pages/Xpress-Mosel.aspx (2012)
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Wang, R., Chakrabarty, K. (2017). ExTest Scheduling and Optimization. In: Testing of Interposer-Based 2.5D Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-54714-5_6
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