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Testing of Interposer-Based 2.5D Integrated Circuits pp 135–162Cite as

ExTest Scheduling and Optimization

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Abstract

A large number of input and output (I/O) ports are available for the dies in a 2.5D IC.

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Notes

  1. 1.

    Those interconnects are tested in the previous test round and thus not considered in the current test round.

  2. 2.

    Note that they cannot share all the input scan channels in order to avoid resulting in untested faults in the combinational logic.

  3. 3.

    Details are not disclosed due to confidentiality reasons.

  4. 4.

    Due to the confidentiality reasons, only A69 and A531 are released for our analysis in this chapter.

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Authors and Affiliations

  1. Nvidia (United States), Sunnyvale, CA, USA

    Ran Wang

  2. Department of ECE, Duke University, Durham, NC, USA

    Krishnendu Chakrabarty

Authors
  1. Ran Wang
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  2. Krishnendu Chakrabarty
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Correspondence to Ran Wang .

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Wang, R., Chakrabarty, K. (2017). ExTest Scheduling and Optimization. In: Testing of Interposer-Based 2.5D Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-54714-5_6

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  • DOI: https://doi.org/10.1007/978-3-319-54714-5_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-54713-8

  • Online ISBN: 978-3-319-54714-5

  • eBook Packages: EngineeringEngineering (R0)

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