Test Architecture and Test-Path Scheduling

  • Ran WangEmail author
  • Krishnendu Chakrabarty


As 2.5D integration emerges as a mainstream technology, test challenges must be adequately addressed in order to address concerns about defect screening.


Proposed Test Architecture Boundary Scan Cells (BSC) Test Path Interconnect Test Small Delay Defects 
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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Nvidia (United States)SunnyvaleUSA
  2. 2.Department of ECEDuke UniversityDurhamUSA

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