Pre-bond Testing of the Silicon Interposer

  • Ran WangEmail author
  • Krishnendu Chakrabarty


In order to minimize the yield loss results from the stacking of good dies on a defective interposer, it is necessary to test the interposer before die stacking.


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  1. 1.
    S.K. Goel, S. Adham, M.-J. Wang, J.-J. Chen, T.-C. Huang, A. Mehta, F. Lee, V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, J. Cho, H. Lee, J. Choi, S. Kim, Test and debug strategy for TSMC CoWoSTM stacking process based heterogeneous 3D IC: a silicon case study, in IEEE International Test Conference, 2013Google Scholar
  2. 2.
    C. Kothandaraman, S.K. Iyer, S.S. Iyer, Electrically programmable fuse (eFUSE) using electromigration in silicides. IEEE Electron Device Lett. 23(9), 523–525 (2002)CrossRefGoogle Scholar
  3. 3.
    H. Suto, S. Mori, M. Kanno, N. Nagashima, Systematic study of the dopant-dependent properties of electrically programmable fuses with silicided poly-si links through a series of I-V measurements. IEEE Trans. Device Mater. Reliab. 7(2), 285–297 (2007). JuneCrossRefGoogle Scholar
  4. 4.
    C. Kothandaraman, S.K. Iyer, S.S. Iyer, Electrically programmable Fuse (eFUSE) using electromigration in silicides. IEEE Electron Device Lett. 23(9), 523–525 (2002). SeptCrossRefGoogle Scholar
  5. 5.
    T. Ueda, H. Takaoka, M. Hamada, Y. Kobayashi, A. Ono, A novel Cu electrical fuse structure and blowing scheme utilizing crack-assisted mode for 90-45 nm-node and beyond, in Symposium on VLSI Technology Digest of Technical Papers, 2006Google Scholar
  6. 6.
    H. Takaoka, T. Ueda, H. Tsuda, A. Ono, A novel via-fuse technology featuring highly stable blow operation with large on-off ratio for 32 nm node and beyond, in IEEE International Electron Devices Meeting, 2007Google Scholar
  7. 7.
    J. Ryckaert, E.J. Marinissen, D. Linten, Two-step interconnect testing of semiconductor dies, 2014. US Patent App. 14/247,019Google Scholar
  8. 8.
    K. Kumagai, Y. Yoneda, H. Izumino, H. Shimojo, M. Sunohara, T. Kurihara, M. Higashi, Y. Mabuchi, A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect, in IEEE Electronic Components and Technology Conference, 2008, pp. 571–576Google Scholar
  9. 9.
    F. Cros, L. Namburi, T. Hu, Fine pitch probes for semiconductor testing and a method to fabricate and assemble same. US Patent 9000793, 2015Google Scholar
  10. 10.
    M.A. Christo, J.A. Maldonado, R.D. Weekly, T. Zhou, Silicon interposer testing for three dimensional chip stack. US Patent 7863106, 2011Google Scholar
  11. 11.
    K.S.-M. Li, S.-J. Wang, J.-L. Wu, C.-Y. Ho, Y. Ho, R.-T. Gu, B.-C. Cheng, Optimized pre-bond test methodology for silicon interposer testing, in IEEE Asian Test Symposium (ATS), 2014, pp. 13–18Google Scholar
  12. 12.
    S. Kannan, R. Agarwal, A. Bousquet, G. Aluri, H.-S. Chang, Device performance analysis on 20 nm technology thin wafers in a 3D package, in IEEE International Reliability Physics Symposium, 2015Google Scholar
  13. 13.
    P.T. Wagner, Interconnect testing with boundary scan, in IEEE International Test Conference, 1987, pp. 52–57Google Scholar
  14. 14.
    L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, W.-T. Cheng, Oscillation-based prebond TSV test. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32(9), 1440–1444 (2013)CrossRefGoogle Scholar
  15. 15.
    D.B. West et al., Introduction to Graph Theory, vol. 2 (Prentice Hall, Upper Saddle River, 2001)Google Scholar
  16. 16.
    M.R. Garey, D.S. Johnson, L. Stockmeyer, Some simplified NP-complete graph problems. Theoret. Comput. Sci. 1(3), 237–267 (1976)CrossRefzbMATHMathSciNetGoogle Scholar
  17. 17.
    R. de Orio, H. Ceric, S. Selberherr, Electromigration failure in a copper dual-damascene structure with a through silicon via. Microelectron. Reliab. 52(9), 1981–1986 (2012)CrossRefGoogle Scholar
  18. 18.
    M. Sunohara, T. Tokunaga, T. Kurihara, M. Higashi, Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring, in IEEE Electronic Components and Technology Conference, 2008, pp. 847–852Google Scholar
  19. 19.
    B. Banijamali, S. Ramalingam, K. Nagarajan, R. Chaware, Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA, in IEEE Electronic Components and Technology Conference, 2011, pp. 285–290Google Scholar
  20. 20.
    H.H. Jones, Technical viability of stacked silicon interconnect technology. Xilinx. White Paper,, 2010
  21. 21.
    P. Dorsey, Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. White Paper, papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf, 2010
  22. 22.
    C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, Post-bond Testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base, in IEEE International Test Conference, 2011Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Nvidia (United States)SunnyvaleUSA
  2. 2.Department of ECEDuke UniversityDurhamUSA

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