Abstract
In this chapter, we will look at modeling sequential logic using the more sophisticated behavioral modeling techniques presented in Chap. 8. We will begin by looking at modeling sequential storage devices. Next, we will look at the behavioral modeling of finite state machines. Finally, we will look at register transfer level, or RTL modeling. The goal of this chapter is to provide an understanding of how hardware description languages can be used to create behavioral models of synchronous digital systems.
Keywords
- Model Sequential Logic
- Verilog Behavioral Model
- Synchronous Digital Systems
- Sensitivity List
- Rising Edge
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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LaMeres, B.J. (2017). Behavioral Modeling of Sequential Logic. In: Introduction to Logic Circuits & Logic Design with Verilog. Springer, Cham. https://doi.org/10.1007/978-3-319-53883-9_9
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DOI: https://doi.org/10.1007/978-3-319-53883-9_9
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-53882-2
Online ISBN: 978-3-319-53883-9
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