Abstract
In the previous chapter, we have shown the test results of NICSLU, where the relative speedups vary in a big range for different benchmarks. In order to understand the performance difference and find possible limiting factors of the scalability, further investigations are required. Toward this goal, in this chapter, we will build a performance model to analyze the performance and find bottlenecks of the scalability of NICSLU.
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Chen, X., Wang, Y., Yang, H. (2017). Performance Model. In: Parallel Sparse Direct Solver for Integrated Circuit Simulation. Springer, Cham. https://doi.org/10.1007/978-3-319-53429-9_7
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DOI: https://doi.org/10.1007/978-3-319-53429-9_7
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-53429-9
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