Skip to main content

A Novel PSO Based Task Scheduling Algorithm for Multi-core Systems

  • Conference paper
  • First Online:
Smart Computing and Communication (SmartCom 2016)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 10135))

Included in the following conference series:

  • 2544 Accesses

Abstract

Multi-core processors have been the mainstream in computer architecture. It also provides the enhancement of the parallelism degree of multiple tasks. An emerged challenge is how to schedule the multiple tasks to the cores for high efficiency. In this paper, a novel task scheduling algorithm is proposed for multi-core systems. This algorithm is based on optimized particle swarm algorithm, which is used to find the optimal solution for the task scheduling. The experimental results have showed that the proposed algorithm can improve the efficiency of task scheduling for multi-core systems.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Khaira, M.S.: Micro-2010: lead performance microprocessor of the year 2010-myth or reality. In: Twelfth International Conference on VLSI Design, pp. 157–163. IEEE Press, Washington, DC (1999)

    Google Scholar 

  2. Olukotun, K., Nayfeh, B.A., Hammond, L., Wilson, K., Chung, K.: The case for a single-chip multiprocessor. ACM SIGOPS Operating Syst. Rev. 30(5), 2–11 (1996)

    Article  Google Scholar 

  3. Nayfeh, B.A., Olukotun, K.: A single-chip multiprocessor. IEEE Comput. 30(9), 79–85 (1997)

    Article  Google Scholar 

  4. Cesario, W., Baghdadi, A., Gauthier L., Lyonnard, D., Nicolescu, G., Paviot, Y., Yoo, S., Jerraya, A.A., Diaz-Nava, M.: Component-based design approach for multicore SoCs. In: Design Automation Conference, pp. 789–794. ACM Press, New York (2002)

    Google Scholar 

  5. Cong, J., Yuan, B.: Energy-efficient scheduling on heterogeneous multi-core architectures. In: 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 345–350. ACM Press, New York (2012)

    Google Scholar 

  6. Das, R., Ausavarungnirun, R., Mutlu, O., Kumar, A., Azimi, M.: Application-to-core mapping policies to reduce memory interference in multi-core systems. In: The 21st International Conference on Parallel Architectures and Compilation Techniques, pp. 455–456. ACM Press, New York (2012)

    Google Scholar 

  7. Åsberg, M., Nolte, T., Kato, S.: Towards partitioned hierarchical real-time scheduling on multi-core processors. SIGBED Rev. 11(2), 13–18 (2014)

    Article  Google Scholar 

  8. Lee, J., Lim, G., Suh, S.: Preemptibility-aware responsive multi-core scheduling. In: The 2011 ACM Symposium on Applied Computing, pp. 748–749. ACM Press, New York (2011)

    Google Scholar 

  9. Fedorova, A.: Operating system scheduling for chip multithreaded processors. Ph.D. thesis, Harvard University (2006)

    Google Scholar 

  10. Zhuang, Y.C., Shieh, C.K., Liang, T.Y., Lee, J.Q.: A group-based load balance scheme for software distributed shared memory systems. J. Supercomput. 28, 295–309 (2004)

    Article  MATH  Google Scholar 

  11. Attiya, G., Hamam, Y.: Two phase algorithm for load balancing in heterogeneous distributed systems. In: 12th Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp. 434–439. IEEE Press, Washington, DC (2004)

    Google Scholar 

  12. Aas, J.: Understanding the Linux 2.6.8.1 CPU scheduler. http://josh.trancesoftware.com/linux/linux_cpu_scheduler.pdf

  13. Ho, W.H., Pinkston, T.M.: A methodology for designing efficient on-chip interconnects on well-behaved communication patterns. In: The 9th International Symposium on High-Performance Computer Architecture, pp. 377–388. IEEE Press, Washington, DC (2003)

    Google Scholar 

  14. Srinivasan, K., Chatha, K.S.: ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis. In: 18th International Conference on VLSI Design, pp. 623–628. IEEE Press, Washington, DC (2005)

    Google Scholar 

  15. Murali, S., Benini, L., Micheli, G.: Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. In: Conference on 2005 Asia and South Pacific Design Automation Conference, pp. 27–32. IEEE Press, Washington, DC (2005)

    Google Scholar 

  16. Ascia, G., Catania, V., Palesi, M.: Multi-objective mapping for mesh-based NoC architectures. In: 2004 International Conference on Hardware/Software Codesign and System Synthesis, pp. 182–187. ACM Press, New York (2004)

    Google Scholar 

  17. Barcelos, D., Brião, E.W., Wagner, F.R.: A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. In: The 20th Annual Conference on Integrated Circuits and Systems Design, pp. 282–287. ACM Press, New York (2007)

    Google Scholar 

  18. Chou, C., Marculescu, R.: User-aware dynamic task allocation in networks-on-chip. In: The Conference on Design, Automation and Test in Europe, pp. 1232–1237. IEEE Press, Washington, DC (2008)

    Google Scholar 

  19. Hu, J., Marculescu, R.: Energy-Aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: The Conference on Design, Automation and Test in Europe, vol. 1, pp. 234–239. IEEE Press, Washington, DC (2004)

    Google Scholar 

  20. Briao, E.W., Barcelos, D., Wronski, F., Wagner, F.R.: Impact of task migration in NoC-based MPSoCs for soft real-time applications. In: IFIP International Conference on Very Large Scale Integration, pp. 296–299. IEEE Press, Washington, DC (2007)

    Google Scholar 

  21. Schor, L., Bacivarov, I., Rai, D., Yang, H., Kang, S.H., Thiele, L.: Scenario-based design flow for mapping streaming applications onto on-chip many-core systems. In: 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 71–80. ACM, New York (2012)

    Google Scholar 

  22. Wang, Y., Liu, H., Liu, D., Qin, Z.W., Shao, Z.L., Sha, E.H.M.: Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip. ACM Trans. Des. Autom. Electron. Syst. 16(2) (2011). Article 14

    Google Scholar 

  23. Zhang, D.S., Guo D.K., Chen, F.Y., Wu, F., Cao, T., Jin, S.Y.: TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks. ACM Trans. Archit. Code Optim. 8(4) (2012). Article 47

    Google Scholar 

  24. Liu, C., Li, J., Rubio, J., Speight, E., Lin, X.Z.: Power-efficient time-sensitive mapping in heterogeneous systems. In: The 21st International Conference on Parallel Architectures and Compilation Techniques, pp. 23–32. ACM Press, New York (2012)

    Google Scholar 

  25. Fu, C., Zhao, Y., Li, M., Xue, C.J.: Maximizing common idle time on multi-core processors with shared memory. In: The 2015 Design, Automation & Test in Europe Conference & Exhibition, pp. 900–903. IEEE Press, Washington, DC (2015)

    Google Scholar 

  26. Dhiman, G., Kontorinis, V., Tullsen, D., Rosing, T., Saxe, E., Chew, J.: Dynamic workload characterization for power efficient scheduling on CMP systems. In: The 16th ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 437–442. ACM Press, New York (2010)

    Google Scholar 

  27. Ma, K., Li, X., Chen, M., Wang, X.R.: Scalable power control for many-core architectures running multi-threaded applications. SIGARCH Comput. Archit. News 39(3), 449–460 (2011)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Wei Hu .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this paper

Cite this paper

Tian, J., Hu, W., Wang, Y., Li, L., Ke, P., Zhang, K. (2017). A Novel PSO Based Task Scheduling Algorithm for Multi-core Systems. In: Qiu, M. (eds) Smart Computing and Communication. SmartCom 2016. Lecture Notes in Computer Science(), vol 10135. Springer, Cham. https://doi.org/10.1007/978-3-319-52015-5_7

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-52015-5_7

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-52014-8

  • Online ISBN: 978-3-319-52015-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics