Abstract
The shrinking feature sizes make transistors increasingly susceptible to soft errors, which can severely degrade the systems’ RAS (Reliability, Availability, and Serviceability). The tough challenge results from not only increasing SER (soft error rate) of storage cells, but also the increasing susceptibility of combinational logics to soft errors. How to efficiently detect soft errors becomes the primary problem in the Backward Error Recovery (BER) schemes that are cost-effective in soft error tolerance. This paper presents a soft error detection scheme, AUDITOR, for flip-flop based pipelines. The AUDITOR copes with both types of soft errors—single event upset (SEU) and single event transient (SET). We propose a “local-audit” fault detection mechanism, by which each pipeline stage is verified independently and the verifying result registers with a dedicated “audit” bit (V-bit). All the V-bits are distributed across the whole pipeline and synergically monitor the pipeline execution. To relax the constraint of SET detection capability imposed by the inherent fully synchronous operation mode in flip-flop based pipelines, we firstly propose using path-compensation technique to address this constraint. Furthermore, a reuse-based design paradigm is employed to reduce the implementation complexity and area overhead. The AUDITOR possesses robust detection capability and short detection latency, at the expense of about \(29\%\) and \(50\%\) increase in area and power consumption, respectively.
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Notes
- 1.
Some researchers view the terminology SEU as the general soft errors: both transient voltage pulses in combinational logics and unintentional bit flip in sequential logics [3]. As many others researchers did, we just take the SEU as unintentional bit flip in this paper, which will not be problematic.
References
Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN), pp. 389–398 (2002)
Nicolaidis, M.: Design for soft error mitigation. IEEE Trans. Device Mater. Reliab. 5(3), 405–418 (2005)
Heidergott, W.: SEU tolerant device, circuit and processor design. In: Proceedings of the 42nd Design Automation Conference (DAC), pp. 5–10 (2005)
Nicolaidis, M.: Time redundancy based soft-error tolerance to rescue nanometer technologies. In: Proceedings of the 17th IEEE VLSI Test Symposium (VTS), pp. 86–94 (1999)
Zyuban, V., Brooks, D., Srinivasan, V., Gschwind, M., Bose, P., Strenski, P.N., Emma, P.G.: Integrated analysis of power and performance for pipelined microprocessors. IEEE Trans. Comput. 53(8), 1004–1016 (2004)
Ernst, D., Kim, N.S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., Mudge, T.: Razor: a low-power pipeline based on circuit-level timing speculation. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 7–18 (2003)
Nicolaidis, M.: GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies. In: Proceedings of the IEEE International Test Conference (ITC), pp. 1–10, October 2007
Sutherland, I., Sproull, R.F., Harris, D.: Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Francisco (1999)
Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edn. Addison Wesley, Boston (2005)
Dodd, P.E., Massengill, L.W.: Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nucl. Sci. 50(3), 583–602 (2003)
Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K.S.: Robust system design with built-in soft-error resilience. IEEE Comput. 38(2), 43–52 (2005)
Das, S., Roberts, D., Lee, S., Pant, S., Blaauw, D., Austin, T., Flautner, K., Mudge, T.: A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circ. 41(4), 792–804 (2006)
Wang, N.J., Patel, S.J.: ReStore: symptom-based soft error detection in microprocessors. IEEE Trans. Dependable Secure Comput. 3(3), 188–201 (2006)
Eaton, P., Benedetto, J., Mavis, D., Avery, K., Sibley, M., Gadlage, M., Turflinger, T.: Single event transient pulsewidth measurements using a variable temporal latch technique. IEEE Trans. Nucl. Sci. 51(6), 3365–3368 (2004)
Saggese, G.P., Wang, N.J., Kalbarczyk, Z.T., Patel, S.J., Iyer, R.K.: An experimental study of soft errors in microprocessors. IEEE Micro 25(6), 30–39 (2005)
Manne, S., Klauser, A., Grunwald, D.: Pipeline gating: speculation control for energy reduction. In: Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), pp. 132–141 (1998)
Sun Microsystem Inc.: OpenSPARC T1 Microarchitecture Specification (2006)
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Zhang, H., Li, Y., Sun, H., Yang, Y. (2017). AUDITOR: A Stage-Wise Soft-Error Detection Scheme for Flip-flop Based Pipelines. In: Qiu, M. (eds) Smart Computing and Communication. SmartCom 2016. Lecture Notes in Computer Science(), vol 10135. Springer, Cham. https://doi.org/10.1007/978-3-319-52015-5_45
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DOI: https://doi.org/10.1007/978-3-319-52015-5_45
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