Abstract
Multi-core architectures may meet the increasing performance requirement of real-time systems. However, it is harder to compute the WCET estimation in multi-core platforms due to inter-task interference that tasks suffer when accessing shared hardware resources. In this paper, we propose a finer grained approach to analyze the inter-task interference for multi-core platforms with the TDMA policy and bank-column cache partitioning, and our approach can reasonably estimate inter-task interference delays. Moreover, we make bank-to-core mapping to optimize the interference delays, and develop an algorithm for finding the best bank-to-core mapping. The experimental results show that our interference analysis approach can improve the tightness of interference delays by 14.68% on average compared to Upper Bound Delay (UBD) approach, and the optimized bank-to-core mapping can achieve the WCET improvement by 9.27% on average.
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Acknowledgements
This work is supported by the National Natural Science Foundation of China(No.61370062,61462004). We thank the anonymous reviewers for their feedback.
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Gan, Z., Zhang, M., Gu, Z., Zhang, J., Tan, H. (2017). Minimizing Bank Conflict Delay for Real-Time Embedded Multicore Systems via Bank Mapping. In: Qiu, M. (eds) Smart Computing and Communication. SmartCom 2016. Lecture Notes in Computer Science(), vol 10135. Springer, Cham. https://doi.org/10.1007/978-3-319-52015-5_2
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DOI: https://doi.org/10.1007/978-3-319-52015-5_2
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