Advanced FPGA-based Fast Linear Convolution

Abstract

Multiple long-tap digital convolutions are sometimes required in different appealing wireless applications, like Massive MIMO system in the 5th generation wireless communications. However, the complexity of such processing system will increase significantly as the number of digital convolution modules is getting larger and the tap of each convolution is growing longer. This chapter will focus on low complexity fast linear convolution approach and its advanced compact FPGA implementation architecture. Starting from SISO-FLC for single-branch processing to MIMO-FLC for multiple-branch processing, we will illustrate the key processing units of FLC approach and how to build an efficient FLC processing core on FPGA. A case study will demonstrate how to utilize MIMO-FLC core to construct a compact spatial multiplexing filter bank for Massive MIMO application and baseband equivalent MIMO channel emulator for the forthcoming 5G wireless networks.