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Solid-State-Drives (SSDs) Modeling pp 67–97Cite as

Design Trade-Offs for NAND Flash-Based SSDs

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Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 58))

Abstract

During the design phase of an SSD, the target application must be always taken into account. In fact, depending on the most important requirements, such as bandwidth, latency or reliability, architecture and cost of the drive might be totally different. Therefore, at the beginning of the development process, a thorough design space exploration is strongly recommended. In this chapter we describe the main actors of the drive architecture and we show how a dedicated CAD tool such as SSDExplorer can be used to optimize the SSD design, given a set of constraints. In particular, we consider 3 different cases: design for maximum bandwidth, design for minimum latency, and performance/reliability trade-off. Of course, in all cases SSD simulations are used to identify the right architecture to achieve the design target, while minimizing the resource request (e.g. number of Flash channels, number of NAND Flash memories, number of processor cores, etc...). For each case, this chapter includes design examples and corresponding simulation results.

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References

  1. An Overview of SSD Write Caching. http://community.spiceworks.com/attachments/post/0013/5918/ssd_write_caching_tech_brief_lo.pdf.

  2. Intel X18-M X25-M SATA Solid State Drive. Enterprise Server/Storage Applications. http://cache-www.intel.com/cd/00/00/42/52/425265_425265.pdf.

  3. Samsung NAND Flash memory K9XXG08UXM series. http://www.arm9board.net/download/fl6410/datasheet/k9g8g08.pdf.

  4. Intel solid-state drive dc s3700 series - quality of service., 2013. http://www.intel.com/content/www/us/en/solid-state-drives/ssd-dc-s3700-quality-service-tech-brief.html.

  5. The cost of latency, 2015. http://www.telx.com/blog/the-cost-of-latency/.

  6. Platform as a service (paas), 2015. http://searchcloudcomputing.techtarget.com/definition/Platform-as-a-Service-PaaS.

  7. R. Micheloni, A. Marelli, and K. Eshghi. Inside Solid State Drives (SSDs). Springer, 2012.

    Google Scholar 

  8. N. Mielke, T. Marquart, Ning Wu, J. Kessenich, H. Belgal, Eric Schares, F. Trivedi, E. Goodness, and L.R. Nevill. Bit error rate in NAND Flash memories. In IEEE International Reliability Physics Symposium (IRPS), pages 9–19, 2008.

    Google Scholar 

  9. Sungjin Lee, Taejin Kim, Kyungho Kim, and Jihong Kim. Lifetime Management of Flash-based SSDs Using Recovery-aware Dynamic Throttling. In USENIX Conference on File and Storage Technologies, (FAST’12), 2012.

    Google Scholar 

  10. Ren-Shuo Liu, Chia-Lin Yang, and Wei Wu. Optimizing NAND Flash-Based SSDs via Retention Relaxation. In USENIX Conference on File and Storage Technologies, (FAST’12), 2012.

    Google Scholar 

  11. Laura M. Grupp, John D. Davis, and Steven Swanson. The Bleak Future of NAND Flash Memory. In USENIX Conference on File and Storage Technologies, (FAST’12), 2012.

    Google Scholar 

  12. Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai. Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling. In Design, Automation Test in Europe Conference (DATE), 2013, pages 1285–1290.

    Google Scholar 

  13. Xueqiang Wang, Guiqiang Dong, Liyang Pan, and Runde Zhou. Error Correction Codes and Signal Processing in Flash Memory, Flash Memories. Igor Stievano (Ed.), 2011.

    Google Scholar 

  14. Intel-Corporation Robert Frickey. Data Integrity on 20nm SSDs. In Flash Memory Summit, 2012.

    Google Scholar 

  15. A.G. Cometti, L.B. Huang, and A. Melik-Martirosian. Apparatus and method for determining a read level of a flash memory after an inactive period of time, February 4 2014. US Patent 8,644,099.

    Google Scholar 

  16. Silicon Motion Jeff Yang. High-Efficiency SSD for Reliable Data Storage Systems. In Flash Memory Summit, 2012.

    Google Scholar 

  17. Youngjoo Lee, Hoyoung Yoo, Injae Yoo, and In-Cheol Park. 6.4gb/s multi-threaded bch encoder and decoder for multi-channel ssd controllers. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 426–428, Feb 2012.

    Google Scholar 

  18. Intel-Corporation Ravi Motwani. Exploitation of RBER Diversity across Dies to Improve ECC Performance in NAND Flash Drive. In Flash Memory Summit, 2012.

    Google Scholar 

  19. Serial ATA International Organization. SATA revision 3.0 specifications. www.sata-io.org.

  20. Nvm express 1.1 specification, 2013. http://nvmexpress.org/wp-content/uploads/2013/05/NVM_Express_1_1.pdf.

  21. Pci express base 3.0 specification, 2013. http://www.pcisig.com/specifications/pciexpress/base3/.

  22. E. Yeo. An LDPC-enabled flash controller in 40nm CMOS. In Proc. of Flash Memory Summit, Aug. 2012.

    Google Scholar 

  23. X. Hu. LDPC codes for flash channel. In Proc. of Flash Memory Summit, Aug. 2012.

    Google Scholar 

  24. Erich F. Haratsch. LDPC Code Concepts and Performance on High-Density Flash Memory. In Proc. of Flash Memory Summit, Aug. 2014.

    Google Scholar 

  25. Tong Zhang. Using LDPC Codes in SSD — Challenges and Solutions. In Proc. of Flash Memory Summit, Aug. 2012.

    Google Scholar 

  26. Kai Zhao, Wenzhe Zhao, Hongbin Sun, Xiaodong Zhang, Nanning Zheng, and Tong Zhang. Ldpc-in-ssd: Making advanced error correction codes work effectively in solid state drives. In Presented as part of the 11th USENIX Conference on File and Storage Technologies (FAST 13), pages 243–256, 2013.

    Google Scholar 

  27. R. Micheloni, A. Marelli and R. Ravasio. Basic coding theory. In Error Correction Codes for Non-Volatile Memories, pages 1–33. Springer-Verlag, 2008.

    Google Scholar 

  28. L. Zuolo, C. Zambelli, P. Olivo, R. Micheloni, and A. Marelli. LDPC Soft Decoding with Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives. In IEEE International Memory Workshop (IMW), pages 1–4, May 2015.

    Google Scholar 

  29. D.H. Nguyen and F.F. Roohparvar. Increased nand flash memory read throughput, March 8 2011. US Patent 7,903,463.

    Google Scholar 

  30. S.H. Lee, S. Bae, J.N. Baek, H.S. Kim, and S.B. Kim. Method of reading data from a non-volatile memory and devices and systems to implement same, March 28 2013. US Patent App. 13/429,326.

    Google Scholar 

  31. N. Shibata, K. Kanda, T. Hisada, K. Isobe, M. Sato, Y. Shimizu, T. Shimizu, T. Sugimoto, T. Kobayashi, K. Inuzuka, N. Kanagawa, Y. Kajitani, T. Ogawa, J. Nakai, K. Iwasa, M. Kojima, T. Suzuki, Y. Suzuki, S. Sakai, T. Fujimura, Y. Utsunomiya, T. Hashimoto, M. Miakashi, N. Kobayashi, M. Inagaki, Y. Matsumoto, S. Inoue, Y. Suzuki, D. He, Y. Honda, J. Musha, M. Nakagawa, M. Honma, N. Abiko, M. Koyanagi, M. Yoshihara, K. Ino, M. Noguchi, T. Kamei, Y. Kato, S. Zaitsu, H. Nasu, T. Ariki, H. Chibvongodze, M. Watanabe, H. Ding, N. Ookuma, R. Yamashita, G. Liang, G. Hemink, F. Moogat, C. Trinh, M. Higashitani, T. Pham, and K. Kanazawa. A 19nm 112.8mm\(^{2}\) 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. In IEEE International Solid-State Circuits Conference (ISSCC), pages 422–424, Feb. 2012.

    Google Scholar 

  32. Daeyeal Lee, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, Young-Ho Lim, and Young-Hyun Jun. A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. In IEEE International Solid-State Circuits Conference (ISSCC), pages 430–432, Feb. 2012.

    Google Scholar 

  33. Hp z640 workstation, 2015. http://www8.hp.com/h20195/v2/GetDocument.aspx?docname=c04434085.

  34. Flexible I/O tester, 2015. http://freecode.com/projects/fio.

  35. J. Kim, E. Lee, J. Choi, D. Lee, and S. Noh. Chip-level raid with flexible stripe size and parity placement for enhanced ssd reliability. IEEE Transactions on Computers, 2014. to appear on.

    Google Scholar 

  36. Xiao-Yu Hu, Evangelos Eleftheriou, Robert Haas, Ilias Iliadis, and Roman Pletka. Write amplification analysis in flash-based solid state drives. In Proceedings of SYSTOR, pages 10:1–10:9, 2009.

    Google Scholar 

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Authors and Affiliations

  1. Dipartimento di Ingegneria, Università degli Studi di Ferrara, via G. Saragat, 1, 44122, Ferrara, Italy

    Lorenzo Zuolo, Cristian Zambelli & Rino Micheloni

  2. Microsemi, Via Torri Bianche 1, 20871, Vimercate, Italy

    Alessia Marelli & Rino Micheloni

  3. Performance Storage Business Unit, Microsemi Corporation, Vimercate, Italy

    Piero Olivo

Authors
  1. Lorenzo Zuolo
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  2. Cristian Zambelli
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  3. Alessia Marelli
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  4. Rino Micheloni
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  5. Piero Olivo
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Corresponding author

Correspondence to Lorenzo Zuolo .

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Editors and Affiliations

  1. NVM Solutions, PMC-Sierra, VIMERCATE, Italy

    Rino Micheloni

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Zuolo, L., Zambelli, C., Marelli, A., Micheloni, R., Olivo, P. (2017). Design Trade-Offs for NAND Flash-Based SSDs. In: Micheloni, R. (eds) Solid-State-Drives (SSDs) Modeling. Springer Series in Advanced Microelectronics, vol 58. Springer, Cham. https://doi.org/10.1007/978-3-319-51735-3_4

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  • DOI: https://doi.org/10.1007/978-3-319-51735-3_4

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  • Online ISBN: 978-3-319-51735-3

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