Skip to main content

PCB Level SI Simulation Based on IBIS Model for FPGA System with DDR2 Memory Devices Application

  • Conference paper
  • First Online:
Book cover Advances in Intelligent Information Hiding and Multimedia Signal Processing

Part of the book series: Smart Innovation, Systems and Technologies ((SIST,volume 64))

  • 1965 Accesses

Abstract

It is essential to perform SI(SI) simulation in the high speed FPGA system with DDR2 memory devices. IBIS model is chosen for simulation because IBIS model could easily be download from website of related integrity circuit(IC) or created according to datasheet of IC. The PCB-level SI simulation flow and analysis methods based on IBIS models are illustrated in this paper, especially some useful application notes. Proper SI simulation which a good guide to routing could solve problems caused by high speed transmission in PCB.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Bob Ross, Syed Huq, Jon Powell, IBIS Models for Signal Integrity Applications, Electrical Engineering Times, A CMP Publication September 2, 1996

    Google Scholar 

  2. Ken Kundert. A Formal Top-Down Design Process for Mixed-Signal Circuits. www.designers-guide.org, 2001,10

  3. Aaron M. Shreeve. Verilog-AMS for Mixed-Signal Integrated Circuits. http://www.cdnusers.org/

  4. Xilinx, Inc. Virtex-4 User Guide. April 10, 2007

    Google Scholar 

  5. Xilinx, Inc. Virtex-4 FPGA Data Sheet:DC and Switching Characteristics. DS302 (v3.2),April 10, 2008

    Google Scholar 

  6. Micron Technology, Inc. the datasheet of DDR2 SDRAM MT47H256M8.2006

    Google Scholar 

  7. Micron Technology, Inc. DDR SDRAM Point-to-Point Simulation Process.2005.07

    Google Scholar 

  8. Micron Technology, Inc. DDR2 Simulation Support. 2005.07

    Google Scholar 

  9. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. JEDEC STANDARD: DDR2 SDRAM SPECIFICATION(JESD79-2C). MAY 2006

    Google Scholar 

  10. Zhou Runjing, Yuan Weiting. Cadence high speed PCB deign and simulation(Rev 2). Publishing house of electronics industry.pp483~714

    Google Scholar 

  11. Micron Technology, Inc. DDR2 SODIMM Optimized Address/Command Nets. 2005

    Google Scholar 

  12. Yu Changsheng, Liu Zhongliang. Timing calculation and Cadence simulation results application. www.cnidz.com. 2007.09.18

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this paper

Cite this paper

Cheng, XY., Zheng, WM. (2017). PCB Level SI Simulation Based on IBIS Model for FPGA System with DDR2 Memory Devices Application. In: Pan, JS., Tsai, PW., Huang, HC. (eds) Advances in Intelligent Information Hiding and Multimedia Signal Processing. Smart Innovation, Systems and Technologies, vol 64. Springer, Cham. https://doi.org/10.1007/978-3-319-50212-0_34

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-50212-0_34

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-50211-3

  • Online ISBN: 978-3-319-50212-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics