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A Systematic Approach to Fault Attack Resistant Design

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Fundamentals of IP and SoC Security

Abstract

Fault injection is a powerful hacking tool, affecting all forms of cryptography. In this chapter, we describe common fault injection mechanisms, and common fault analysis techniques. From these observations, we derive a set of guidelines and techniques for fault attack resistant design. The main objective of this contribution is to describe fault attack resistant design and differentiate it from fault tolerant design, a set of techniques based on redundancy. The key differentiator between the two types of design can be made by considering the cause of the fault. Fault tolerant design deals with random, arbitrary events and generic failures of a design. In contrast, fault attack resistant design deals with an intelligent adversary who has a focused objective to break the security of a design. The fault tolerant methods basically require the system to be able to continue performing its functions correctly in presence of faults. On the other hand, a fault attack resistant design requires the system to continue performing its intended operation without leaking secret data-dependent information in presence of faults. While fault tolerant design techniques can be used to create a fault attack resistant design, in this chapter, will show that by analyzing the fault attack requirements, the nature of the threat enables significant optimizations, which improve cost and performance of the protected designs. We review several fault-resistant design techniques that are generic and broadly applicable to secure intellectual property (IP) modules.

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Acknowledgements

This research was supported through the National Science Foundation Grant 1441710, and through the Semiconductor Research Corporation.

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Authors and Affiliations

  1. Virginia Tech, Blacksburg, USA

    Nahid Farhady Galathy, Bilgiday Yuce & Patrick Schaumont

Authors
  1. Nahid Farhady Galathy
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  2. Bilgiday Yuce
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  3. Patrick Schaumont
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Correspondence to Nahid Farhady Galathy .

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Editors and Affiliations

  1. University of Florida , Gainesville, Florida, USA

    Swarup Bhunia

  2. NXP Semiconductors (United States) , Austin, Texas, USA

    Sandip Ray

  3. Advanced Computing and Microelectronics, Indian Statistical Institute, Kolkata, India

    Susmita Sur-Kolay

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Galathy, N.F., Yuce, B., Schaumont, P. (2017). A Systematic Approach to Fault Attack Resistant Design. In: Bhunia, S., Ray, S., Sur-Kolay, S. (eds) Fundamentals of IP and SoC Security. Springer, Cham. https://doi.org/10.1007/978-3-319-50057-7_9

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  • DOI: https://doi.org/10.1007/978-3-319-50057-7_9

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  • Online ISBN: 978-3-319-50057-7

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