Abstract
Modern designs like system-on-chips and network-on-chips are equipped with variety of resources such as memory blocks in different sizes and types, interfaces with different characteristics, and several processors and co-processors to realize high performance and reliable computing systems, often with tight design restrictions in terms of power and area. The high complexity of modern designs, the constraint of time-to-market window, and the cost restriction of final product highly drive the horizontal integrated circuit design process. Practicing the horizontal integrated circuit design process, however, exposes a design to various types of malicious modifications that shall cause malfunctions under very rare circumstances. This chapter discusses integrated circuit supply chain globalization and threats across the integrated circuit design flow. In the following, existing techniques for hardware Trojan detection based on side-channel analyses, logic values, and without golden model are reviewed. Circuit vulnerabilities at different levels are studied and techniques for design-for-hardware-trust are presented. The chapter concludes with a discussion on hardware Trojans in complex designs and existing challenges on the path for hardware Trojan detection and prevention.
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References
Ernst&Young: Global semiconductor industry study. http://www.indabook.org/preview/37zGj6ryslpY95ZaVcT_D8zdtr5D-X-sWb6GMXsJzhQ,/Global-semiconductor-industry-study-report-Ernst-amp-Young.html?query=Cloud-Computing-Landscape-and-Research-Challenges
http://www.reportlinker.com/p 02070028-summary/Semiconductor-Silicon-IP-Market-by-Form-Factor-Integrated-Circuit-IP-SOC-IP-Design-Architecture-Hard-IP-Soft-IP-Processor-Type-Microprocessor-DSP-Application-Geography-and-Verification-IP-Forecast-Analysis-to.html
Saleh, R., Mirabbasi, S., Lemieux, G., Pande, P.P., Grecu, C., Ivanov, A.: System-on-Chip: Reuse and Integration. Proc. IEEE 94(6), 1050–1069 (2006)
Morales, M., Rau, S., Palma, M.J., Venkatesan, M., Pulskamp, F., Dugar, A.: industry developments and models. Intelligent Systems: The Next Big Opportunity. International Data Corporation (2011)
Greaves, D.J.: System on Chip Design and Modelling. University of Cambridge, Computer Laboratory. Lecture Notes (2011)
Hardee, P.: The five facets of SoC design complexity. http://www.eetimes.com/document.asp?doc_id=1277891
Avizienis, A., Laprie, J., Randell, B., Landwehr, C.: Basic concepts and taxonomy of dependable and secure computing. IEEE Trans. Dependable Secure Comput. 1(1), 11–33 (2004)
Villasenor, J.: Compromised By Design? Securing the Defense Electronics Supply Chain. The Center for Technology Innovation at Brookings (2013)
Johnson, B., Freeman, D., Christensen, D., Wang, S.T.: Market Trends: Rising Costs of Production Limit Availability of Leading-Edge Fabs. GARTNER, INC. http://www.gartner.com/DisplayDocument?doc_cd=238123. Accessed 1 Sept 2012
Villasenor, J., Tehranipoor, M.: The Hidden Dangers of Chop-Shop Electronics. In: IEEE Spectrum. http://spectrum.ieee.org/semiconductors/processors/the-hidden-dangers-of-chopshop-electronics (2013)
Wang, L., Wu, C., Touba, N.: VLSI Test Principles and Architectures: Design for Testability. Morgan Kaufmann Publishers (2006)
Adee, S.: The Hunt for the Kill Switch. In: IEEE Spectrum. http://www.spectrum.ieee.org/print/6171 (2008)
Tehranipoor, M., Koushanfar, F.: A survey of hardware Trojan taxonomy and detection. IEEE Des. Test Comput. 27(1), 10–25 (2010)
Wang, X., Tehranipoor, M., Plusquellic, J.: Detecting malicious inclusions in secure hardware: challenges and solutions. In: Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, pp. 15–19 (2008)
Xiao, K., Zhang, X., Tehranipoor, M.: A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Des. Test 30(2), 26–34 (2013)
Li, J., Lach, J.: At-speed delay characterization for IC authentication and Trojan horse detection. In: Proceedings of IEEE International Symposium Hardware-Oriented Security and Trust, pp. 8–14 (2008)
Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., Sunar, B.: Trojan detection using IC fingerprinting. In: Proceedings of the Symposium on Security and Privacy, pp. 296–310 (2007)
Wang, X., Salmani, H., Tehranipoor, M., Plusquellic, J.: Hardware Trojan detection and isolation using current integration and localized current analysis. In: Proceedings of the International Symposium on Fault and Defect Tolerance in VLSI Systems, pp. 87–95 (2008)
Huang, H., Bhunia, S., Mishra, P.: MERS: statistical test generation for side-channel analysis based Trojan detection. In: ACM Conference on Computer and Communications Security (CCS), Vienna, Austria, 24–28 Oct 2016
Ferraiuolo, A., Zhang, X., Tehranipoor, M.: Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90 nm ASIC. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 37–42 (2012)
Rajendran, J., Jyothi, V., Sinanoglu, O., Karri, R.: Design and analysis of ring oscillator based design-for-Trust technique. In: Proceedings of IEEE VLSI Test Symposium, pp. 105–110 (2011)
Rad, R., Plusquellic, J., Tehranipoor, M.: A sensitivity analysis of power signal methods for detecting hardware trojans under real process and environmental conditions. IEEE Trans. Very Large Scale Integr. Syst. 18(12), 1735–1744 (2010)
Narasimhan, S., Yueh, W., Wang, X., Mukhopadhyay, S., Bhunia, S.: Improving IC security against Trojan attacks through integration of security monitors. IEEE Des. Test Comput. 29(5), 37–46 (2012)
Karimian, N., Tehranipoor, F., Rahman, M.T., Kelly, S., Forte, D.: Genetic algorithm for hardware Trojan detection with ring oscillator network (RON). 2015 IEEE International Symposium on Technologies for Homeland Security (HST), Waltham, MA, pp. 1–6 (2015)
Narasimhan, S., Du, D., Chakraborty, R.S., Paul, S., Wolff, F., Papachristou, C., Roy, K., Bhunia, S.: Hardware Trojan detection by multiple-parameter side-channel analysis. IEEE Trans. Comput. 62(11), 2183–2195 (2013)
Hu, K., Nowrozy, A.N., Reday, S., Koushanfar, F.: High-sensitivity hardware Trojan detection using multimodal characterization. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1271–1276 (2013)
Koushanfa, F., Mirhoseini, A.: A Unified framework for multimodal submodular integrated circuits Trojan detection. IEEE Trans. Inf. Forensics Secur. 6(1), 162–174 (2011)
Potkonjak, M., Nahapetian, A., Nelson, M., Massey, T.: Hardware Trojan horse detection using gate-level characterization. In: Proceedings of Design Automation Conference, pp. 688–693 (2009)
Alkabani, Y., Koushanfar, F.: Consistency-based characterization for IC Trojan detection. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 123–127 (2009)
Wolff, F., Papachristou, C., Bhunia, S., Chakraborty, R.S.: Towards Trojan free trusted ICs: problem analysis and detection scheme. In: Proceedings of ACM Design, Automation and Test in Europe Conference, pp. 1362–1365 (2008)
Voyiatzis, A.G., Stefanidis, K.G., Kitsos, P.: Efficient triggering of Trojan hardware logic. In: 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, pp. 1–6 (2016)
Li, M., Davoodi, A., Tehranipoor, M.: A sensor-assisted self-authentication framework for hardware Trojan detection. IEEE Des. Test 30(5), 74–82 (2013)
Narasimhan, S., Wang, X., Du, D., Chakraborty, R.S., Bhunia, S.: TeSR: A robust temporal self-referencing approach for hardware trojan detection. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 71–74 (2011)
Hicks, M., Finnicum, M., King, S.T., Martin, M., Smith, J.M.: Overcoming an untrusted computing base: detecting and removing malicious hardware automatically. In: IEEE Symposium on Security and Privacy, pp. 64–77 (2010)
Zhang, J., Yuan, F., Wei, L., Sun, Z., Xu, Q.: VeriTrust: verification for hardware trust. In: ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 61:1–61:8 (2013)
Waksman, A., Suozzo, M., Sethumadhavan, S.: FANCI: identification of stealthy malicious logic using Boolean functional analysis. In: Proceedings of the 2013 ACM SIGSAC Conference on Computer & Communications Security (CCS), pp. 697–708 (2013)
Çakir, B., Malik, S.: Hardware Trojan detection for gate-level ICs using signal correlation based clustering. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 471–476 (2015)
Oya, M., Shi, Y., Yanagisawa, M., Togawa, N.: A score-based classification method for identifying hardware-Trojans at gate-level Netlists. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 465–470 (2015)
Salmani, H., Tehranipoor, M., Karri, R.: On design vulnerability analysis and trust benchmark development. In: IEEE International Conference on Computer Design (ICCD) (2013)
Xiao, K., Tehranipoor, M.: BISA: Built-in self-authentication for preventing hardware Trojan insertion. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 45–50 (2013)
Tehranipoor, M., Salmani, H., Zhang, X.: Integrated Circuit Authentication Hardware Trojans and Counterfeit Detection. Springer (2014)
Salmani, H., Tehranipoor, M., Plusquellic, J.: A novel technique for improving hardware Trojan detection and reducing trojan activation time. In: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(1), 112–125 (2012)
Salmani, H., Tehranipoor, M.: Layout-aware switching activity localization to enhance hardware trojan detection. IEEE Trans. Inf. Forensics Secur. 7(1), 76–87 (2012)
Wang, X., Zheng, Y., Basak, A., Bhunia, S.: IIPS: infrastructure IP for secure SoC design. IEEE Trans. Comput. 64(8), 2226–2238 (2015)
Jayashankara Shridevi, R., Rajamanikkam, C., Chakraborty, K., Roy, S.: Catching the Flu: emerging threats from a third party power management unit. In: 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, pp. 1–6 (2016)
Frey, J., Yu, Q.: A hardened network-on-chip design using runtime hardware Trojan mitigation methods. Integration (VLSI J.) (2016)
Kulkarni, A., Pino, Y., French, M., Mohsenin, T.: 2016. Real-time anomaly detection framework for many-core router through machine-learning techniques. J. Emerg. Technol. Comput. Syst. 13(1) Article 10 (June 2016), 22 pp. doi:http://dx.doi.org/10.1145/2827699
Mokhoff, N., Wallace, R.: Outsourcing trend proves: complex by design. EE Times. http://www.eetimes.com/document.asp?doc_id=1152570 (2005)
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Salmani, H. (2017). Hardware Trojan Attacks and Countermeasures. In: Bhunia, S., Ray, S., Sur-Kolay, S. (eds) Fundamentals of IP and SoC Security. Springer, Cham. https://doi.org/10.1007/978-3-319-50057-7_10
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DOI: https://doi.org/10.1007/978-3-319-50057-7_10
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