# Robust Analog Arithmetic Based on the Continuous Valued Number System

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## Abstract

In this chapter fundamentals of Continuous Valued Number System (CVNS) are presented. This number system has been developed for analog arithmetic, and has been applied in implementing a series of mixed-signal neural networks. The CVNS multi-digit representation of analog values allows flexibility in implementation of analog circuits and reduces the demand on the accuracy requirements of analog implementations. Continuous values can be presented by a set of analog-digits. Analog-digits have information overlap with each other, which can be used for detection or correction of errors caused by implementation or arithmetic issues. The level of information overlap between the digits is the designer choice and can be adjusted based on the design requirements. Higher overlap between the digits means errors can be corrected to a higher degree; however, area and power requirements of the system increase. In this chapter principles of digit generation, CVNS addition, and CVNS multiplication are presented.

## Notes

### Acknowledgements

The authors would like to acknowledge the use of the following source material.

• Parts of Sect. 7.5: Copyright © IEEE. All rights reserved. Reprinted, with permission, from B. Zamanlooy, A. Novak, M. Mirhassani, “Complexity Study of the Continuous Valued umber System Adders,” IEEE International Symposium on Multiple Valued Logic, 116–121, 2012.

• Sections 7.6 and 7.7: Copyright © IEEE. All rights reserved. Reprinted, with permission, from “CVNS Synapse Multiplier for Robust Neurochips with On-Chip Learning,” *IEEE Transaction on Very Large Scale Integration (VLSI) System*, Vol. 23, No. 11, pp. 2540–2551, 2015.

## References

- 1.I.M. Thoidis, D. Soudris, J.M. Fernandez, A. Thanailakis, The circuit design of multiple-valued logic voltage-mode adders, in
*Proceedings of IEEE International Symposium on Circuits and Systems*, vol. 4 (2001), pp. 162–165Google Scholar - 2.M.C. Mekhallalati, M.K. Ibrahim, A new high radix maximally redundant signed digit adder, in
*Procedings of IEEE International Symposium on Circuits and Systems*, vol. 1 (1999), pp. 459–462Google Scholar - 3.A. Saed, M. Ahmadi, G.A. Jullien, A number system with continuous valued digits and modulo arithmetic. IEEE Trans. Comput.
**51**(11), 1294–1304 (2002)CrossRefMathSciNetGoogle Scholar - 4.A. Saed, M. Ahmadi, G.A. Jullien, W.C. Miller, Overlap resolution: arithmetic with continuous valued digits for hybrid architectures, in
*IEEE Asilomar Conference on Signals, Systems and Computers*, vol. 2 (1997), pp. 1188–1191Google Scholar - 5.A. Saed, M. Ahmadi, G.A. Jullien, W.C. Miller, Overlap resolution: arithmetic with continuous valued digits for hybrid architectures, in
*Proceeding of IEEE Midwest Symposium on Circuits and Systems*(1997), pp. 377–380Google Scholar - 6.A. Saed, M. Ahmadi, G.A. Jullien, W.C. Miller, Circuit tolerances and word lengths in Overlap resolution, in
*IEEE International Symposium on Circuits and Systems*(1998), pp. 197–200Google Scholar - 7.A. Saed, M. Ahmadi, G.A. Jullien, W.C. Miller, Arithmetic circuit analog digits, in
*IEEE International Symposium on Multiple Valued Logic*(1999), pp. 186–191Google Scholar - 8.R. Aroca, M. Ahmadi, R. Hashemian, G.A. Jullien, A B-compliment continuous valued digit adder, in
*Proceeding of IEEE 9th International Conference on Electronics, Circuits and Systems*, vol. 2 (2002), pp. 433–436Google Scholar - 9.M. Mirhassani, M. Ahmadi, G.A. Jullien, Digital multiplication using continuous valued digits, in
*IEEE International Symposium on Circuits and Systems (ISCAS)*(2007), pp. 3263–3266Google Scholar - 10.M. Mirhassani, M. Ahmadi, G.A. Jullien, Reconfigurable 64-bit binary adder based on continuous digits. IEEE Trans. Very Large Scale Integr. VLSI Syst.
**16**(9), 1141–1150 (2008)CrossRefGoogle Scholar - 11.G. Khodabandehloo, M. Mirhassani, M. Ahmadi, CVNS-based storage and refreshing scheme for a multi-valued dynamic memory. IEEE Trans. Very Large Scale Integr. VLSI Syst.
**19**(8), 1517–1521 (2011)Google Scholar - 12.B. Zamanlooy, M. Mirhassani, CVNS synapse multiplier for Robust neurochips with on-chip learning. IEEE Trans. Very Large Scale Integr. VLSI Syst.
**23**(11), 2540–2551 (2015)CrossRefGoogle Scholar - 13.M. Mirhassani, M. Ahmadi, G.A. Jullien, 16-bit radix-4 continuous valued digit adders,
*Conference on Advanced Signal Processing, Algorithms, Architectures, and Implementations XVI, SPIE Symposium*, ID 631302 (2006)Google Scholar - 14.B. Zamanlooy, A. Novak, M. Mirhassani, Complexity study of the continuous valued umber system adders, in
*IEEE International Symposium on Multiple Valued Logic*(2012), pp. 116–121Google Scholar - 15.J.F. Ramos, A. Gago, Two operand binary adders with threshold logic. IEEE Trans. Comput.
**48**(12), 1324–1337 (1999)CrossRefMathSciNetGoogle Scholar - 16.K. Asanovir, N. Morgan, Experimental determination of precision requirements for back-propagation training of artificial neural networks, in
*2nd International Conference on Microelectronics for Neural Network*(1991), pp. 9–15Google Scholar - 17.J. Holi, J.-N. Hwang, Finite precision error analysis of neural network hardware implementations. IEEE Trans. Comput.
**42**(3), 281–290 (1993)Google Scholar