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RNS-Based Embedded Processor Design

  • Pedro Miguens MatutinoEmail author
  • Ricardo Chaves
  • Leonel Sousa
Chapter
  • 782 Downloads

Abstract

In this chapter a unified architecture providing a generic, programmable, and scalable RNS computation based on {2 n ± k i } moduli channels is described. This architecture allows for the design of RNS with an arbitrarily long moduli set of the form {2 n ± k0, ⋯ , 2 n ± k j }, with \(j \in \mathbb{N}_{0}^{+}\). The considered moduli set allows to arbitrarily increase the number of RNS channels and consequently increasing the Dynamic Range (DR) or reducing the width of the channels, leading to a reduction in delay and area cost of the arithmetic operations, allowing to further exploit the RNS parallelism. The proposed RNS architecture provides not only a programmable processor capable of supporting a wide range of algorithms using RNS, but also a tool for researchers to evaluate new algorithms, moduli sets, and conversion approaches.

Keywords

Computer arithmetic Residue Number System (RNS) Generic modular arithmetic Parallel computation Binary-to-RNS conversion RNS-to-binary conversion Processor 

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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Pedro Miguens Matutino
    • 1
    Email author
  • Ricardo Chaves
    • 2
  • Leonel Sousa
    • 2
  1. 1.ISEL - IPLINESC-IDLisboaPortugal
  2. 2.IST - Universidade de Lisboa, INESC-IDLisboaPortugal

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