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Introduction to Residue Number System: Structure and Teaching Methodology

  • Amir Sabbagh MolahosseiniEmail author
  • Leonel Sousa
Chapter
  • 845 Downloads

Abstract

The emergence of embedded systems with severe power restrictions together with technology developments that require fault-tolerant approaches spurred interest in the residue number system (RNS). Owing to its unique characteristics, which lead to fast and low-power arithmetic circuits, RNS has become an interesting option to design embedded systems for nowadays high-performance applications. However, to unlock the full potential of RNS for designing efficient embedded systems, the system’s architect should be aware of the structure and latest advances on RNS circuits and systems, including residue arithmetic, algorithms, and hardware design. RNS has a multi-disciplinary nature supported on mathematical formulation, digital design, and computer architecture. This chapter briefly reviews the most up to date hardware structures of RNS components, and introduces the most efficient designs for each part to ease the designer’s work. Moreover, a teaching method to learn about RNS-based systems, usable both for class lecturing and individual research, is presented. All aspects of RNS, namely moduli set selection, residue-based hardware component design, including forward and reverse converters, and modulo arithmetic circuits are considered in a comprehensive teaching approach. This teaching methodology can lead to a deeper understanding of RNS, and consequently open the gates to perform more effective and applicable investigation on RNS-based embedded systems.

Keywords

Computer arithmetic Residue number system Parallel processing Modular adder Digital design Digital signal processing 

References

  1. 1.
    P. Marwedel, Embedded system design: embedded systems foundations of cyber-physical systems (Springer International Publishing, Dordrecht, 2011)CrossRefzbMATHGoogle Scholar
  2. 2.
    S. Yang, Toward a wireless world. IEEE Technol. Soc. Mag. 26(2), 32–42 (2007)CrossRefGoogle Scholar
  3. 3.
    H.L. Garner, The residue number system. IRE Trans. Electron. Comput. 8(2), 140–147 (1959)CrossRefGoogle Scholar
  4. 4.
    T. Stouraitis, V. Paliouras, Considering the alternatives in low-power design. IEEE Circuits Devices 7, 23–29 (2001)Google Scholar
  5. 5.
    C.H. Chang, A.S. Molahosseini, A.A.E. Zarandi, T.F. Tay, Residue number systems: a new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circuits Syst. Mag. 15(4), 26–44 (2015)CrossRefGoogle Scholar
  6. 6.
    P.V.A. Mohan, Residue number systems: Algorithms and architectures (Kluwer, Boston, 2002)CrossRefGoogle Scholar
  7. 7.
    A. Omondi, B. Premkumar, Residue number systems: Theory and implementations (Imperial College Press, London, 2007)CrossRefzbMATHGoogle Scholar
  8. 8.
    J. Chen, J. Hu, Energy-efficient digital signal processing via voltage-over scaling-based residue number system. IEEE Trans. Very Large Scale Integr. Syst. 21(7), 1322–1332 (2013)CrossRefGoogle Scholar
  9. 9.
    S. Antão, L. Sousa, The CRNS framework and its application to programmable and reconfigurable cryptography. ACM Trans. Archit. Code Optim. 9(4), 1–33 (2013)CrossRefGoogle Scholar
  10. 10.
    L. Sousa, S.F. Antão, P.S.A. Martins, Combining residue arithmetic to design efficient cryptographic circuits and systems. IEEE Circuits Syst. Mag., to appear, 2016Google Scholar
  11. 11.
    T.F. Tay, C.H. Chang, A non-iterative multiple residue digit error detection and correction algorithm in RRNS. IEEE Trans. Comput. 65(2), 396–408 (2016)CrossRefMathSciNetGoogle Scholar
  12. 12.
    R. Ye1, A. Boukerche, H. Wang, X. Zhou, B. Yan, RESIDENT: a reliable residue number system-based data transmission mechanism for wireless sensor networks, Springer Wireless Netw., to appear, 2016Google Scholar
  13. 13.
    X. Zheng, B. Wang, C. Zhou, X. Wei, Q. Zhang, Parallel DNA arithmetic operation with one error detection based on 3-moduli set, IEEE Trans. Nano Biosci., to appear, 2016Google Scholar
  14. 14.
    A. Celesti, M. Fazio, M. Villari, A. Puliafito, Adding long-term availability, obfuscation, and encryption to multi-cloud storage systems. J. Netw. Comput. Appl. 59, 208–218 (2016)CrossRefGoogle Scholar
  15. 15.
    M. Esmaeildoust, D. Schinianakis, H. Javashi, T. Stouraitis, K. Navi, Efficient RNS implementation of elliptic curve point multiplication over GF(p). IEEE Trans. Very Large Scale Integr. Syst. 21(8), 1545–1549 (2013)CrossRefGoogle Scholar
  16. 16.
    Y. Liu, E.M.K. Lai, Moduli set selection and cost estimation for RNS-based FIR filter and filter bank design. Des. Autom. Embedded Syst. 9, 123–139 (2004)CrossRefGoogle Scholar
  17. 17.
    M. Dasygenis, I. Petrousov, A generic moduli selection algorithm for the residue number system, in Proceedings of International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015Google Scholar
  18. 18.
    A. Persson, L. Bengtsson, Forward and reverse converters and moduli set selection in signed-digit residue number systems. J. Signal Process. Syst. 56(1), 1–15 (2009)CrossRefGoogle Scholar
  19. 19.
    J.C. Bajard, M. Kaihara, T. Plantard, Selected RNS bases for modular multiplication, in Proceedings of the 19th IEEE symposium on Computer Arithmetic, 2009Google Scholar
  20. 20.
    J. Ramírez, U. Meyer-Bäse, F. Taylor, A. García, A. Lloris, Design and implementation of high-performance RNS wavelet processors using custom IC technologies. J. VLSI Signal Process. Syst. Signal Image Video Technol. 34(3), 227–237 (2003)CrossRefzbMATHGoogle Scholar
  21. 21.
    F. Gandino, F. Lamberti, G. Paravati, J.C. Bajard, P. Montuschi, An algorithmic and architectural study on montgomery exponentiation in RNS. IEEE Trans. Comput. 61(8), 1071–1083 (2012)CrossRefMathSciNetGoogle Scholar
  22. 22.
    K. Navi, A.S. Molahosseini, M. Esmaeildoust, How to teach residue number system to computer scientists and engineers. IEEE Trans. Educ. 54(1), 156–163 (2011)CrossRefGoogle Scholar
  23. 23.
    F. Pourbigharaz, H.M. Yassine, Simple binary to residue transformation with respect to 2/sup m/+1 moduli. IEE Proc. Circuits Devices Syst. 141(6), 522–526 (1994)CrossRefGoogle Scholar
  24. 24.
    S. Piestrak, Design of residue generators and multioperand modular adders using carry-save adders. IEEE Trans. Comput. 43(1), 68–77 (1994)CrossRefzbMATHGoogle Scholar
  25. 25.
    A.B. Premkumar, E.L. Ang, E.M.-K. Lai, Improved memoryless RNS forward converter based on the periodicity of residues. IEEE Trans. Circuits Syst. II Express Briefs 53(2), 133–137 (2006)CrossRefGoogle Scholar
  26. 26.
    C. Efstathiou, N. Moschopoulos, K. Tsoumanis, K. Pekmestzi, On the design of configurable modulo 2^n ± 1 residue generators, in Proceedings of euromicro conference on digital system design (DSD), 2012, pp. 50–56Google Scholar
  27. 27.
    H.T. Vergos, D. Bakalis, C. Efstathiou, Fast modulo 2n + 1 multi-operand adders and residue generators. Integr. VLSI J. 43(1), 42–48 (2010)CrossRefGoogle Scholar
  28. 28.
    A.A. Hiasat, Arithmetic binary to residue encoders for moduli (2n ± 2k + 1). IEE Proc. Comput. Digit. Tech. 150(6), 369–374 (2003)CrossRefGoogle Scholar
  29. 29.
    P.M. Matutino, R. Chaves, L. Sousa, Arithmetic-based binary-to-RNS converter modulo (2n ± k) for jn-bit dynamic range. IEEE Trans. Very Large Scale Integr. Syst. 23(3), 603–607 (2015)CrossRefGoogle Scholar
  30. 30.
    K. Shirakawa, T. Uemura, Y. Iguchi, A realization method of forward converters from multiple-precision binary numbers to residue numbers with arbitrary mutable modulus, in Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL), 2011Google Scholar
  31. 31.
    G. Petrousov, M. Dasygenis, A unique network EDA tool to create optimized ad hoc binary to residue number system converters, in Proceedings of International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014.Google Scholar
  32. 32.
    J.Y.S. Low, C.H. Chang, A new approach to the design of efficient residue generators for arbitrary moduli. IEEE Trans. Circuits and Syst.–I 60(9), 2366–2374 (2013)CrossRefMathSciNetGoogle Scholar
  33. 33.
    R. Zimmermann, Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication, in Proceedings of the IEEE International Symposium on Computer Arithmetic, 1999, pp. 158–167.Google Scholar
  34. 34.
    L. Kalampoukas et al., High-speed parallel-prefix modulo 2n − 1 adders. IEEE Trans. Comput. 49(7), 673–680 (2000)CrossRefGoogle Scholar
  35. 35.
    R.A. Patel, M. Benaissa, S. Boussakta, Fast parallel-prefix architectures for modulo 2n − 1 addition with a single representation of zero. IEEE Trans. Comput. 56(11), 1484–1492 (2007)CrossRefMathSciNetGoogle Scholar
  36. 36.
    R. Muralidharan, C.H. Chang, Radix-8 booth encoded modulo 2n − 1 multipliers with adaptive delay for high dynamic range residue number system. IEEE Trans. Circuits Syst.–I 58(5), 982–993 (2011)CrossRefMathSciNetGoogle Scholar
  37. 37.
    L.S. Didier, L. Jaulmes, Fast modulo 2n − 1 and 2n + 1 adder using carry-chain on FPGA, in Proc. of Asilomar Conference on Signals, Systems and Computers, 2013, pp. 1155–1159Google Scholar
  38. 38.
    R. Muralidharan, C.H. Chang, Area-power efficient modulo 2n − 1 and modulo 2n + 1 multipliers for {2n − 1, 2n, 2n + 1} based RNS. IEEE Trans. Circuits Syst.–I 59(10), 2263–2274 (2012)CrossRefMathSciNetGoogle Scholar
  39. 39.
    H.T. Vergos, G.N. Dimitrakopoulos, On modulo 2n + 1 adder design. IEEE Trans. Comput. 61(2), 173–186 (2012)CrossRefMathSciNetGoogle Scholar
  40. 40.
    H.T. Vergos, Area-time efficient end-around inverted carry adders. Integr. VLSI J. 45(4), 388–394 (2012)CrossRefGoogle Scholar
  41. 41.
    S.M. Mirhosseini, A.S. Molahosseini, M. Hosseinzadeh, L. Sousa, P. Martins, A reduced-bias approach with a lightweight hard-multiple generator to design radix-8 modulo 2n + 1 multiplier. IEEE Trans. Circuits Syst.-II, to appear, 2016Google Scholar
  42. 42.
    C.H. Chang, S. Menon, B. Cao, T. Srikanthan, A configurable dual moduli multi-operand modulo adder, in Proceedings of IEEE International Symposium on Circuits and Systems, 2005, pp. 1630–1633Google Scholar
  43. 43.
    E. Vassalos, D. Bakalis, H.T. Vergos, On the design of modulo 2n ± 1 subtractors and adders/subtractors. Circuits Syst. Signal Process. 30(6), 1445–1461 (2011)CrossRefGoogle Scholar
  44. 44.
    C. Efstathiou, K. Tsoumanis, K. Pekmestzi, I. Voyiatzis, Modulo 2n ± 1 fused add-multiply units, in Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 91–96Google Scholar
  45. 45.
    H.T. Vergos, D. Bakalis, Area-time efficient multi-modulus adders and their applications. Microprocessors Microsystems Embedded Hardware Des. 36(5), 409–419 (2012)CrossRefGoogle Scholar
  46. 46.
    R. Muralidharan, C.H. Chang, Radix-4 and radix-8 Booth encoded multi-modulus multipliers. IEEE Trans. Circuits Syst.–I 60(11), 2940–2952 (2013)CrossRefGoogle Scholar
  47. 47.
    H. Pettenghi, S. Cotofana, L. Sousa, Efficient method for designing modulo {2n ± K} multipliers. J. Circuits Syst. Comput. 23(1), 1450001 (2014)CrossRefGoogle Scholar
  48. 48.
    G. Jaberipur, S.H.F. Langroudi, (4 + 2\log n)\delta G parallel prefix modulo—(2n − 3) adder via double representation of residues in [0, 2]. IEEE Trans. Circuits Syst.-II 62(6), 583–587 (2015)CrossRefGoogle Scholar
  49. 49.
    S. Ma, J.H. Hu, C.H. Wang, A novel modulo 2n − 2k − 1 adder for residue number system. IEEE Trans. Circuits Syst.-I 60(11), 2962–2972 (2013)CrossRefGoogle Scholar
  50. 50.
    J.L. Beuchat, Some modular adders and multipliers for field programmable gate arrays, in Proceedings of Parallel and Distributed Processing Symposium, 2003, pp. 1–8Google Scholar
  51. 51.
    R.A. Patel, M. Benaissa, N. Powell, S. Boussakta, Novel power-delay-area-efficient approach to generic modular addition. IEEE Trans. Circuits Syst.-I 54, 1279–1292 (2007)CrossRefGoogle Scholar
  52. 52.
    H. Nakahara, T. Sasao, A deep convolutional neural network based on nested residue number system, in Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–6Google Scholar
  53. 53.
    Y. Wang, X. Song, M. Aboulhamid, H. Shen, Adder based residue to binary numbers converters for (2n − 1, 2n, 2n + 1). IEEE Trans. Signal Process. 50(7), 1772–1779 (2002)CrossRefMathSciNetGoogle Scholar
  54. 54.
    P.V.A. Mohan, RNS-to-binary converter for a new three-moduli set {2n+1 − 1, 2n, 2n − 1}. IEEE Trans. Circuits Syst.-II 54(9), 775–779 (2007)CrossRefGoogle Scholar
  55. 55.
    A. Hariri, K. Navi, R. Rastegar, A new high dynamic range moduli set with efficient reverse converter. J. Comput. Math. Appl. 55(4), 660–668 (2008)CrossRefzbMATHMathSciNetGoogle Scholar
  56. 56.
    A.S. Molahosseini, K. Navi, O. Hashemipour, A. Jalali, An efficient architecture for designing reverse converters based on a general three-moduli set. J. Syst. Archit. 54, 929–934 (2008)CrossRefGoogle Scholar
  57. 57.
    R. Chaves, L. Sousa, Improving RNS multiplication with more balanced moduli sets and enhanced modular arithmetic structures. IET Comput. Digital Tech. 1(5), 472–480 (September 2007)Google Scholar
  58. 58.
    P. Patronik, S.J. Piestrak, Design of reverse converters for general RNS moduli sets {2k, 2n − 1, 2n + 1, 2n+1 − 1} and {2k, 2n − 1, 2n + 1, 2n−1 − 1} (n even). IEEE Trans. Circuits Syst.-I 61(6), 1687–1700 (2014)CrossRefGoogle Scholar
  59. 59.
    A.A.E. Zarandi, A.S. Molahosseini, M. Hosseinzadeh, S. Sorouri, S.F. Antão, L. Sousa, Reverse converter design via parallel-prefix adders: novel components, methodology and implementations. IEEE Trans. Very Large Scale Integr. Syst. 23(2), 374–378 (2015)CrossRefGoogle Scholar
  60. 60.
    A.S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei, S. Timarchi, Efficient reverse converter designs for the new 4-moduli sets {2n − 1, 2n, 2n + 1, 22n+1 − 1} and {2n − 1, 2n + 1, 22n, 22n + 1} based on new CRTs. IEEE Trans. Circuits Syst.-I 57(4), 823–835 (2010)CrossRefMathSciNetGoogle Scholar
  61. 61.
    L. Sousa, S. Antao, MRC-based RNS reverse converters for the four-moduli sets {2n + 1, 2n − 1, 2n, 22n+1 − 1} and {2n + 1, 2n − 1, 22n, 22n+1 − 1}. IEEE Trans. Circuits Syst. II 59(4), 244–248 (2012)CrossRefGoogle Scholar
  62. 62.
    H. Pettenghi, R. Chaves, L. Sousa, RNS reverse converters for moduli sets with dynamic ranges up to (8n + 1)-bit. IEEE Trans. Circuits Syst. I 60(6), 1487–1500 (2013)CrossRefMathSciNetGoogle Scholar
  63. 63.
    C.C.H. Chang, T. Srikanthan, A residue-to-binary converter for a new 5-moduli set. IEEE Trans. Circuits Syst.–I 54(5), 1041–1049 (2007)CrossRefMathSciNetGoogle Scholar
  64. 64.
    M.H. Sheu, S.H. Lin, C. Chen, S.W. Yang, An efficient VLSI design for a residue to binary converter for general balance moduli {2n − 1, 2n + 1, 2n − 3, 2n + 3}. IEEE Trans. Circuits Syst.-II 51(3), 152–155 (2004)CrossRefGoogle Scholar
  65. 65.
    A.A.E. Zarandi, A.S. Molahosseini, L. Sousa, M. Hosseinzadeh, An efficient component for designing signed reverse converters for a class of RNS moduli sets with composite form {2K, 2P-1}, IEEE Trans. Very Large Scale Integr. Syst., to appear, 2016Google Scholar
  66. 66.
    L.C. Tai, C.F. Chen, Technical note. Overflow detection in a redundant residue number system. IEE Proc. Comput. Digital Tech. 131(3), 97–98 (1984)CrossRefGoogle Scholar
  67. 67.
    D. Younes, P. Steffan, Universal approaches for overflow and sign detection in residue number system based on {2n–1, 2n, 2n + 1}, in Proceedings of Eighth International Conference on Systems, 2013, pp. 77–81Google Scholar
  68. 68.
    C.H. Chang, J.Y.S. Low, Simple, fast and exact RNS scaler for the three-moduli set {2n − 1, 2n, 2n + 1}. IEEE Trans. Circuits Syst.–I 58(11), 2686–2697 (2011)CrossRefMathSciNetGoogle Scholar
  69. 69.
    T.F. Tay, C.H. Chang, J.Y.S. Low, Efficient VLSI implementation of 2n scaling of signed integer in RNS {2n − 1, 2n, 2n + 1}. IEEE Trans. Very Large Scale Integr. Syst. 21(10), 1936–1940 (2013)CrossRefGoogle Scholar
  70. 70.
    L. Sousa, 2n RNS scalers for extended 4-moduli sets. IEEE Trans. Comput. 64(12), 3322–3334 (2015)CrossRefMathSciNetGoogle Scholar
  71. 71.
    S. Kumar, C.H. Chang, A new fast and area-efficient adder-based sign detector for RNS {2n − 1, 2n, 2n + 1}. IEEE Trans. Very Large Scale Integr. Syst. 24(7), 2608–2612 (2016)CrossRefGoogle Scholar
  72. 72.
    L. Sousa, P.S.A. Martins, Efficient sign identification engines for integers represented in the RNS extended 3-moduli set {2n − 1, 2n+k, 2n + 1}. Electron. Lett. 50(16), 1138–1139 (2014)CrossRefGoogle Scholar
  73. 73.
    M. Xu, Z. Bian, R. Yao, Fast sign detection algorithm for the rns moduli set {2n+1 − 1, 2n − 1, 2n}. IEEE Trans. Very Large Scale Integr. Syst. 23(2), 379–383 (2015)CrossRefGoogle Scholar
  74. 74.
    Z. Torabi, G. Jaberipur, Low-power/cost rns comparison via partitioning the dynamic range. IEEE Trans. Very Large Scale Integr. Syst. 24(5), 1849–1857 (2016)CrossRefGoogle Scholar
  75. 75.
    L. Sousa, P.S.A. Martins, sign detection and number comparison on rns 3-moduli sets {2n − 1, 2n+x, 2n + 1}, Circuits Syst. Signal Process., to appear, 2016Google Scholar
  76. 76.
    S. Kumar, C.H. Chang, T.F. Tay, New algorithm for signed integer comparison in {2n + k, 2n − 1, 2n + 1, 2n ± 1 − 1} and its efficient hardware implementation, IEEE Trans. Circuits Syst.–I, to appear, 2016Google Scholar
  77. 77.
    R. Chokshi, K.S. Berezowski, A. Shrivastava, S.J. Piestrak, Exploiting residue number system for power-efficient digital signal processing in embedded processors, in Proceedings of the International conference on Compilers, architecture, and synthesis for embedded systems, 2009, pp. 19–28Google Scholar
  78. 78.
    S.F. Antão, J.C. Bajard, L. Sousa, RNS based elliptic curve point multiplication for massive parallel architectures. Comput. J. 55(5), 629–647 (2012)CrossRefGoogle Scholar
  79. 79.
    E. Vassalos, D. Bakalis, CSD-RNS-based single constant multipliers. J. Signal Process. Syst. 67(3), 255–268 (2012)CrossRefGoogle Scholar
  80. 80.
    J.S. Chiang, M. Lu, Floating-point numbers in residue number systems. Comput. Math. Appl. 22(10), 127–140 (1991)CrossRefzbMATHMathSciNetGoogle Scholar
  81. 81.
    C.H. Vun, A.B. Premkumar, W. Zhang, A new RNS based DA approach for inner product computation. IEEE Trans. Circuits Syst.-I 60(8), 2139–2152 (2013)CrossRefMathSciNetGoogle Scholar
  82. 82.
    O. Abdelfattah, Data conversion in residue number system, M.E. Thesis, Department of Electrical and Computer Engineering, McGill University, Montreal, 2011Google Scholar
  83. 83.
    N.Z. Haron, S. Hamdioui, Redundant residue number system code for fault-tolerant hybrid memories. ACM J. Emerging Technol. Comput. Syst. 7(1), 19 (2011)Google Scholar

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© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Department of Computer EngineeringKerman Branch, Islamic Azad UniversityKermanIran
  2. 2.Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento (INESC-ID), Instituto Superior Técnico (IST), Universidade de LisboaLisbonPortugal

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