Skip to main content
SpringerLink
Log in

Reconfigurable Multiprocessor Systems-on-Chip

  • Chapter
  • First Online:
Computing Platforms for Software-Defined Radio

  • 1367 Accesses

Abstract

Software Defined Radios (SDRs) require architectures with a high flexibility to support multi-mode and multi-standard receivers and transmitters. In addition, these architectures need to fulfill the contradicting requirements of high performance for processing high data rates and low power consumption to be deployable in mobile devices. As the market for SDR is evolving, a scalable and adaptive architecture is desired to be able to upgrade the architecture to provide the needed computing performance for future use cases. This chapter highlights the requirements of high flexibility, high performance, low power, and high scalability and presents a solution to fulfill these requirements using runtime reconfigurable Multi-Processor Systems-on-Chip (MPSoCs).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Reed, J.: Software Radio - A Modern Approach to Radio Engineering. Prentice-Hall, Englewood, Cliffs, NJ (2002)

    Google Scholar 

  2. Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34 (2), 171–210 (2002)

    Article  Google Scholar 

  3. Radunovic, B.: An overview of advances in reconfigurable computing systems. In: Proceedings of the 32nd Hawaii International Conference on System Science (1999)

    Google Scholar 

  4. Hauck, S., DeHon, A.: Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann Series in Systems on Silicon. Morgan Kaufmann Publishers Inc., San Francisco, CA (2007)

    MATH  Google Scholar 

  5. Becker, J.: Configurable systems-on-chip: commercial and academic approaches. In: Proceedings of the IEEE 9th International Conference on Electronics, Circuits and Systems (ICECS 2002), Dubrovnik (Kroatien), vol. 2, pp. 809–812, September 2002

    Google Scholar 

  6. Synopsys Inc.: CHIPit Platinum Edition and HAPS-600 Series Hardware Reference Manual (v.1.9) (2012). Available at: www.synopsys.com

  7. Cadence: Cadence Rapid Prototyping Platform. Datasheet (2011). Available at: www.synopsys.com

  8. Angermeier, J., Goehringer, D., Majer, M., Teich, T., Fekete, S., van der Veen, J.: The Erlangen slot machine-a platform for interdisciplinary research in reconfigurable computing. Inf. Technol. J. Oldenbourg Wissenschaftsverlag 49 (3), 143–148 (2007)

    Google Scholar 

  9. Huebner, M., Goehringer, D., Noguera, J., Becker, J.: Fast dynamic and partial reconfiguration Data Path with low Hardware overhead on Xilinx FPGAs. In: Proceedings of the IEEE International Symposium on Parallel and Distributed Processing, Workshops and PhD Forum (IPDPSW), April 2010

    Google Scholar 

  10. Kao, C.: Benefits of partial reconfiguration. Xcell J. Fourth Quarter, 65–67 (2005)

    Google Scholar 

  11. Uhm, M.: Software-defined radio: the new architectural paradigm. Xilinx DSP Magazin, 40–42 (2005)

    Google Scholar 

  12. Becker, T., Luk, W., Cheung, P.Y.K.: Parametric design for reconfigurable software-defined radio. In: Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), pp. 15–26, March 2009

    Google Scholar 

  13. Delahaye, J.P., Palicot, J., Moy, C., Leray, P.: Partial reconfiguration of FPGAs for dynamical reconfiguration of a software radio platform. In: Proceedings of the 16th IST Mobile and Wireless Communications Summit, pp. 1–5, July 2007

    Google Scholar 

  14. Dobson, C., Rooks, K., Athanas, P.: A power-efficient FPGA-based self-adaptive soft-ware defined radio. In: Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1–8 (2014)

    Google Scholar 

  15. Flynn, M.J.: Very high-speed computing systems. Proc. IEEE 54 (12), 1901–1909 (1966)

    Article  Google Scholar 

  16. Goehringer, D., Huebner, M., Perschke, T., Becker, J.: A taxonomy of reconfigurable single/multi-processor systems-on-chip. Hindawi Int. J. Reconfig. Comput., 2009 (395018), pp. 1–11 (2009)

    Article  Google Scholar 

  17. Goehringer, D.: Flexible Design and Dynamic Utilization of Adaptive Scalable Multi-Core Systems. Dissertation, Karlsruhe Institute of Technology, Verlag Dr. Hut Muenchen (2011)

    Google Scholar 

  18. Hartenstein, R.: Stonewalled progress of computing efficiency: why we must reinvent computing. In: Keynote, 25th Symposium on Integrated Circuits and Systems Design (SBCCI) (2012)

    Google Scholar 

  19. Paulsson, K., Huebner, M., Zou, H., Becker, J.: Realization of real-time control flow oriented automotive applications on a soft-core multiprocessor system based on Xilinx Virtex-II FPGAs. In: Proceedings of International Workshop on Applied Reconfigurable Computing (ARC), pp. 103–110 (2005)

    Google Scholar 

  20. Huebner, M., Paulsson, K., Becker, J.: Parallel and flexible multiprocessor system-on-chip for adaptive automotive applications based on Xilinx MicroBlaze Soft-Cores. In: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2005)

    Google Scholar 

  21. Claus, C., Stechele, W., Herkersdorf, A.: Autovision - a run-time reconfigurable MPSoC architecture for future driver assistance systems? Inf. Technol. J. 49 (3), 181–187 (2007)

    Google Scholar 

  22. Bobda, C., Haller, T., Muehlbauer, F., Rech, D., Jung, S.: Design of adaptive multiprocessor on chip systems. In: Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design (SBCCI), pp. 177–183 (2007)

    Google Scholar 

  23. Tumeo, A., Regazzoni, F., Palermo, G., Ferrandi, F., Sciuto, D.: A reconfigurable multiprocessor architecture for a reliable face recognition implementation. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) (2010)

    Google Scholar 

  24. Nguyen, T.D.A., Kumar, A.: PR-HMPSoC: a versatile partially reconfigurable heterogeneous multiprocessor system-on-chip for dynamic FPGA-based embedded systems. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2014)

    Google Scholar 

  25. Yang, Z.J., Kumar, A., Ha, Y.: An area-efficient dynamically reconfigurable spatial division multiplexing network-on-chip with static throughput guarantee. In: Proceedings of the International Conference in Field-Programmable Technology (FPT), pp. 389–392 (2010)

    Google Scholar 

  26. Cappelli, A., Lodi, A., Mucci, C., Toma, M., Campi, F.: A dataflow control unit for C-to-configurable pipelines compilation flow. In: Proceedings of IEEE 12th International Symposium on Field-Programmable Customs Computing Machines (FCCM), Napa Valley (CA), pp. 332–333 (2004)

    Google Scholar 

  27. Berekovic, M., Kanstein, A., Mei, B.: Mapping MPEG video decoders on the ADRES reconfigurable array processor for next generation multi-mode mobile terminals. In: Proceedings of Global Signal Processing Conferences and Expos for the Industry: TV to Mobile (GSPX) (2006)

    Google Scholar 

  28. Sander, O., Braun, L., Becker, J.: An exploitation of data reallocation by performing internal FPGA self-reconfiguration mechanisms. In: Proceedings of Reconfigurable Computing: Architectures, Tools and Applications (ARC), pp. 312–317 (2008)

    Google Scholar 

  29. Shelburne, M., Patterson, C., Athanas, P., Jones, M., Martin, B., Fong, R.: Metawire: using FPGA configuration circuitry to emulate a network-on-chip. In: Proceedings of Field Program-mable Logic and Applications (FPL), pp. 257–262 (2008)

    Google Scholar 

  30. Pionteck, T., Albrecht, C., Koch, R., Maehle, E., Huebner, M., Becker, J.: Communication architectures for dynamically reconfigurable FPGA designs. In: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS) (2007)

    Google Scholar 

  31. Braun, L., Huebner, M., Becker, J., Perschke, T., Schatz, V., Bach, S.: Circuit-switched run-time adaptive network-on-chip for image processing applications. In: Proceedings of the International Conference on Field Programmable Logic and Application (FPL), pp. 688–691 (2007)

    Google Scholar 

  32. Goehringer, D., Oey, O., Huebner, M., Becker, J.: Heterogeneous and runtime parameterizable star-wheels network-on-chip. In: Proceedings of 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS X) (2011)

    Google Scholar 

  33. Rettkowski, J., Goehringer, D.: RAR-NoC: a reconfigurable and adaptive routable network-on-chip for FPGA-based multiprocessor systems. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) (2014)

    Google Scholar 

  34. Goehringer, D., Huebner, M., Schatz, V., Becker, J.: Runtime adaptive multi-processor system-on-chip: RAMPSoC. In: Proceedings of the IEEE International Symposium Parallel and Distributed Processing (IPDPS), pp. 1–7 (2008)

    Google Scholar 

  35. Goehringer, D., Werner, S., Huebner, M., Becker, J.: RAMPSoCVM: runtime support and hardware virtualization for a runtime adaptive MPSoC. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2011)

    Google Scholar 

  36. Goehringer, D., Meder, L., Werner, S., Oey, O., Becker, J., Huebner, M.: Adaptive multi-client network-on-chip memory core: hardware architecture, software abstraction layer and application exploration. Hindawi Int. J. Reconfig. Comput., 2012 (298561) pp. 1–14 (2012)

    Article  Google Scholar 

  37. Oey, O.,Werner, S., Goehringer, D., Stuckert, A., Becker, J., Huebner, M.: Virtualization of heterogeneous and adaptive multi-core /multi-board systems. In: Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP) (2012)

    Google Scholar 

  38. Goehringer, D., Huebner, M., Benz, M., Becker, J.: A Design methodology for application partitioning and architecture development of reconfigurable multiprocessor systems-on-chip. In: Proceedings of the 18th International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2010)

    Google Scholar 

  39. MathWorks: Real-Time Workshop Embedded Coder. Available at: www.mathworks.de

  40. GCC: the GNU Compiler Collection. Available at: gcc.gnu.org

  41. Kernighan, B.W., Lin, S.: An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 49 (12), 291–307 (1970)

    Article  MATH  Google Scholar 

  42. Fiduccia, C.M., Mattheyses, R.M.: A linear-time heuristic for improving network partitions. In: Proceedings of the 19th Design Automation conference (DAC), pp. 175–181 (1982)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Ruhr-University Bochum (RUB), Bochum, Germany

    Diana Goehringer

Authors
  1. Diana Goehringer
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Diana Goehringer .

Editor information

Editors and Affiliations

  1. Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland

    Waqar Hussain

  2. Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland

    Jari Nurmi

  3. Communication Systems laboratory, Department of Information Technology, University of Turku , Turku, Finland

    Jouni Isoaho

  4. Fraunhofer IIS , Nürnberg, Germany

    Fabio Garzia

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Goehringer, D. (2017). Reconfigurable Multiprocessor Systems-on-Chip. In: Hussain, W., Nurmi, J., Isoaho, J., Garzia, F. (eds) Computing Platforms for Software-Defined Radio. Springer, Cham. https://doi.org/10.1007/978-3-319-49679-5_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-49679-5_5

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-49678-8

  • Online ISBN: 978-3-319-49679-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation