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The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio

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Computing Platforms for Software-Defined Radio

Abstract

The advancement in performance of mobile devices goes hand in hand with increasing demand for communication bandwidth. In the past decade an almost unmanageable number of different wireless communication standards has emerged. In addition, the complexity of many of those standards has led to a steadily increasing demand for high performance modem signal processing. Future SDR baseband processing can significantly benefit from the massive parallelism provided by homogeneous many-core architectures. In this chapter, the CoreVA-MPSoC is presented as an example of an embedded hierarchical multiprocessor architecture for SDR processing. Parallelism is introduced at different levels of the CoreVA-MPSoC: basic building block is the resource-efficient VLIW processor CoreVA, providing fine-grained concurrency at the instruction level. Multiple CoreVA CPUs are combined within a CPU cluster and connected via a high speed, low latency interconnect. Finally, a dedicated Network on Chip is used to combine an arbitrary number of CPU clusters on a single chip. In addition to the hardware architecture, an MPSoC compiler for streaming applications is presented and utilized for the mapping of SDR applications to the CoreVA-MPSoC under throughput, latency, energy, and memory constraints.

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Notes

  1. 1.

    VLIW: Very Long Instruction Word.

  2. 2.

    NoC: Network-on-Chip.

  3. 3.

    MIMO: Multiple Input, Multiple Output.

  4. 4.

    DMA: Direct Memory Access.

  5. 5.

    SIMD: Single Instruction, Multiple Data.

  6. 6.

    RISC: Reduced Instruction Set Computing.

  7. 7.

    MAC: Multiply Accumulate.

  8. 8.

    ALU: Arithmetic Logic Unit.

  9. 9.

    NUMA: Non-Uniform Memory Access.

  10. 10.

    FIFO: First In First Out.

  11. 11.

    STMicroelectronics, 10 metal layer, Worst Case Corner: 1.0 V, 125 ∘C.

  12. 12.

    ULP: Ultra Low Power.

  13. 13.

    OFDM: Orthogonal Frequency-Division Multiplexing.

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Acknowledgements

This research was supported by the ATN—DAAD Joint Research Co-operation Scheme: Tightly Coupled Software Tools and Adaptable Hardware for Resource Efficient Multiprocessor Architectures, the DFG CoE 277: Cognitive Interaction Technology (CITEC), and the German Federal Ministry of Education and Research (BMBF) within the projects KogniHome (16SV7054K), Treufunk (16KISO236), and the Leading-Edge Cluster “Intelligent Technical Systems OstWestfalenLippe” (it’s OWL), managed by the Project Management Agency Karlsruhe (PTKA). The authors are responsible for the contents of this publication.

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Authors and Affiliations

  1. Cognitronics and Sensor Systems Group, CITEC, Bielefeld University, Bielefeld, Germany

    Gregor Sievers, Boris Hübener, Johannes Ax, Martin Flasskamp, Thorsten Jungeblut & Mario Porrmann

  2. Science and Engineering Faculty,, Queensland University of Technology, Brisbane, QLD, Australia

    Wayne Kelly

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  1. Gregor Sievers
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  6. Thorsten Jungeblut
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Editors and Affiliations

  1. Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland

    Waqar Hussain

  2. Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland

    Jari Nurmi

  3. Communication Systems laboratory, Department of Information Technology, University of Turku , Turku, Finland

    Jouni Isoaho

  4. Fraunhofer IIS , Nürnberg, Germany

    Fabio Garzia

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Sievers, G. et al. (2017). The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio. In: Hussain, W., Nurmi, J., Isoaho, J., Garzia, F. (eds) Computing Platforms for Software-Defined Radio. Springer, Cham. https://doi.org/10.1007/978-3-319-49679-5_3

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  • DOI: https://doi.org/10.1007/978-3-319-49679-5_3

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