Abstract
This work presents an efficient Feild Programmable Gate Array (FPGA) based local filter design for portable and high speed image processing applications. It is highly optimized by using two level optimization. The first level optimization at design-level exploits tempo-spatial parallelism of filters by developing parallel/pipelined architecture. For exploiting spatial-parallelism, design computes partial results of multiple MACs in parallel and accumulates them via adder-tree for final result. Though it bears good performance aptitude but adder-tree incurs long critical path (4.713 ns) thus limits design performance. The critical path was reduced to 2.489 ns with temporal parallelism by pipelining the adder-tree. Design performance is further enhanced by deploying the second level optimization at post-implementation level where device aware floor-planning fine tunes the design. It aligns all utilized embedded resources of design on Xilinx Virtex-5 device and confines slice based logic across them. It results in packing the design within small area with reduced slice count and critical path (2.32 ns). After applying two levels of optimization, the design occupies 89 Slices, 3 DSP-Slices, 2 BRAM18 and achieves high frequency of 431.03 MHz.
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References
Bailey, D.G.: Design for Embedded Image Processing on FPGAs. John Wiley & Sons, Singapore (2011)
Betz, V., Rose, J., Marquardt, A.: Architecture and CAD for Deep-Submicron FPGAs, vol. 497. Springer Science & Business Media, New York (2012)
Elamaran, V., Praveen, A., Reddy, M.S., Aditya, L.V., Suman, K.: FPGA implementation of spatial image filters using Xilinx system generator. Proc. Eng. 38, 2244–2249 (2012)
Gonzalez, R.C., Woods, R.E.: Digital Image Processing. Prentice Hall, Upper Saddle River (2002)
Hasan, S., Yakovlev, A., Boussakta, S.: Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator. In: 2010 7th International Symposium on Communication Systems Networks and Digital Signal Processing (CSNDSP), pp. 765–769. IEEE (2010)
Hedberg, H.: Image processing architectures for binary morphology and labeling. Lund University (2008)
Xilinx Inc.: Virtex-5 FPGA xtremedsp design considerations user guide, January 2009
Xilinx Inc.: Virtex-5 FPGA User Guide v5.4 (2012)
Kazmi, M., Aziz, A., Akhtar, P., Kundi, D.E.S.: FPGA based compact and efficient full image buffering for neighborhood operations. Adv. Electr. Comput. Eng. 15(1), 95–104 (2015)
Kiran, M., War, K.M., Kuan, L.M., Meng, L.K., Kin, L.W.: Implementing image processing algorithms using hardware in the loop approach for Xilinx FPGA. In: International Conference on Electronic Design, ICED 2008, pp. 1–6. IEEE (2008)
Moreo, A.T., Lorente, P.N., Valles, F.S., Muro, J.S., Andrs, C.F.: Experiences on developing computer vision hardware algorithms using Xilinx system generator. Microprocess. Microsyst. 29(8), 411–419 (2005)
Oklobdzija, V.G.: The Computer Engineering Handbook. CRC Press, Boca Raton (2001)
Perri, S., Lanuzza, M., Corsonello, P., Cocorullo, G.: A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsyst. 29(8), 381–391 (2005)
Said, Y., Saidani, T., Smach, F., Atri, M.: Real time hardware co-simulation of edge detection for video processing system. In: 2012 16th IEEE Mediterranean Electrotechnical Conference (MELECON), pp. 852–855. IEEE (2012)
Said, Y., Saidani, T., Smach, F., Atri, M., Snoussi, H.: Embedded real-time video processing system on FPGA. In: Elmoataz, A., Mammass, D., Lezoray, O., Nouboud, F., Aboutajdine, D. (eds.) ICISP 2012. LNCS, vol. 7340, pp. 85–92. Springer, Heidelberg (2012). doi:10.1007/978-3-642-31254-0_10
Saidani, T., Atri, M., Dia, D., Tourki, R.: Using Xilinx system generator for real time hardware co-simulation of video processing system. In: Ao, S.-L., Gelman, L. (eds.) Electronic Engineering and Computing Technology. LNEE, vol. 60, pp. 227–236. Springer, Netherlands (2010)
Samarawickrama, M.G.: Performance Evaluation of Vision Algorithms on FPGA. Universal-Publishers (2010)
Sudeep, K., Majumdar, J.: A novel architecture for real time implementation of edge detectors on FPGA. Int. J. Comput. Sci. Issues 8(1), 193–202 (2011)
Wasfy, W., Zheng, H.: General structure design for fast image processing algorithms based upon FPGA DSP slice. Phys. Proc. 33, 690–697 (2012)
Woods, R., McAllister, J., Lightbody, G., Yi, Y.: FPGA-Based Implementation of Signal Processing Systems. Wiley Online Library (2008)
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Kazmi, M., Aziz, A., Akhtar, P., Ikram, N. (2017). A FPGA Based Two Level Optimized Local Filter Design for High Speed Image Processing Applications. In: Akagi, M., Nguyen, TT., Vu, DT., Phung, TN., Huynh, VN. (eds) Advances in Information and Communication Technology. ICTA 2016. Advances in Intelligent Systems and Computing, vol 538. Springer, Cham. https://doi.org/10.1007/978-3-319-49073-1_5
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