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Low Power ECC Implementation on ASIC

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Advances in Information and Communication Technology (ICTA 2016)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 538))

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Abstract

In this paper, the Low power Elliptic Curve Cryptography (ECC) structure over Galois field \(GF({2^m})\) is studied and implemented on the Application Specific Integrated Circuit (ASIC) tool for wireless sensor network and Internet of Things (IoT) Applications. Clock gating technique is used for decreasing power consumption. The implementation is conducted by the 180 nm CMOS standard library shows that the proposed ECC structure has the power consumption of 10.4 \(\upmu \)W/MHz outweigh than previous designs.

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Correspondence to Van-Lan Dao .

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Dao, VL., Nguyen, VT., Hoang, VP. (2017). Low Power ECC Implementation on ASIC. In: Akagi, M., Nguyen, TT., Vu, DT., Phung, TN., Huynh, VN. (eds) Advances in Information and Communication Technology. ICTA 2016. Advances in Intelligent Systems and Computing, vol 538. Springer, Cham. https://doi.org/10.1007/978-3-319-49073-1_36

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  • DOI: https://doi.org/10.1007/978-3-319-49073-1_36

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-49072-4

  • Online ISBN: 978-3-319-49073-1

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