Abstract
In this paper, an FPGA-based Mel Frequency Cepstral Coefficient (MFCC) IP core for speech recognition is presented. The implementation results on FPGA show that the proposed MFCC core achieves higher resource usage efficiency compared with other designs.
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Dao, VL., Nguyen, VD., Nguyen, HD., Hoang, VP. (2017). Hardware Implementation of MFCC Feature Extraction for Speech Recognition on FPGA. In: Akagi, M., Nguyen, TT., Vu, DT., Phung, TN., Huynh, VN. (eds) Advances in Information and Communication Technology. ICTA 2016. Advances in Intelligent Systems and Computing, vol 538. Springer, Cham. https://doi.org/10.1007/978-3-319-49073-1_27
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DOI: https://doi.org/10.1007/978-3-319-49073-1_27
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