Abstract
Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-to-market constraints. It is crucial to ensure that an IP block is not vulnerable to input conditions that violate its non-functional (parametric) constraints, such as power, temperature, or performance. Power supply voltages, increased integration densities, and higher operating frequencies, among other factors, are producing devices that are more sensitive to power dissipation and reliability problems. Power viruses which have excessive power dissipation can lead to overheating, electromigration, and a reduced chip lifetime. Moreover, large instantaneous power consumption causes voltage drop and ground bounce, resulting in circuit delays and soft errors. As a result, reliability analysis of worst-case peak power and peak temperature has steadily become a critical part of the design process of digital circuits.
Keywords
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
R. Bertran, A. Buyuktosunoglu, M.S. Gupta, M. González, P. Bose, Systematic energy characterization of cmp/smt processor systems via automated micro-benchmarks, in Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, December (2012), pp. 199–211
CPUburn-in. http://cpuburnin.com/
N.E. Evmorfopoulos, G.I. Stamoulis, J.N. Avaritsiotis. A Monte Carlo approach for maximum power estimation based on extreme value theory. IEEE Trans. Comput. Aided Des. 21 (4), 415–432 (2002).
K. Ganesan, L.K. John, MAximum Multicore POwer (MAMPO): an automatic multithreaded synthetic power virus generation framework for multicore systems, in Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage ACM International Conference for High Performance Computing, Networking, Storage and Analysis, Article No. 53 (2011)
K. Ganesan, J. Jo, W.L. Bircher, D. Kaseridis, Z. Yu, L.K. John, System-level Max Power (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks. in The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010
H. Hajimiri, P. Mishra, S. Bhunia, Dynamic cache tuning for efficient memory based computing in multicore architectures, in International Conference on VLSI Design, 2013
H. Hajimiri, K. Rahmani, P. Mishra, Efficient peak power estimation using probabilistic cost-benefit analysis, in International Conference on VLSI Design, Bengaluru, January 3–7, 2015
M.S. Hsiao, E.M. Rudnick, J.H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, in IEEE International Symposium on Low Power Electronics and Design, 1997
M.S. Hsiao, E.M. Rudnick, J.H. Patel, Effects of delay models on peak power estimation of VLSI sequential circuits, in Proceedings of the 1997 IEEE/ACM International Conference on Computer-aided Design, 1997
M.S. Hsiao, E.M. Rudnick, J.H. Patel, Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8 (4), 435–439 (2000)
Y. Huang, P. Mishra, Reliability and energy-aware cache reconfiguration for embedded systems, in IEEE International Symposium on Quality Electronic Design, 2016
A.M. Joshi, L. Eeckhout, L.K. John, C. Isen, Automated microprocessor stressmark generation, in IEEE 14th International Symposium on High Performance Computer Architecture (HPCA) (2008), pp. 229–239 (2008)
Y. Kim, L.K. John, S. Pant, S. Manne, M. Schulte, W.L. Bircher, M.S.S. Govindan, AUDIT: stress testing the automatic way, in 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) December (2012), pp. 212–223
H. Mangassarian, A. Veneris, F. Najm, Maximum circuit activity estimation using pseudo-Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2), 271–284 (2012)
MPrime, wikipedia page. https://en.wikipedia.org/wiki/Prime95
K. Najeeb, V.V.R. Konda, S.K.S. Hari, V. Kamakoti, V.M. Vedula, Power virus generation using behavioral models of circuits, in 25th IEEE VLSI Test Symposium (VTS’07), Berkeley, CA (2007), pp. 35–42
K. Najeeb, K. Gururaj, V. Kamakoti, V. Vedula, Controllability-driven power virus generation for digital circuits, in IEEE 20th International Conference on VLSI Design (VLSID) (2007), pp. 407–412
X. Qin, W. Wang, P. Mishra, TCEC: temperature- and energy-constrained scheduling in real-time multitasking systems. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. (TCAD) 31 (8), 1159–1168 (2012)
K. Rahmani, P. Mishra, S. Bhunia, Memory-based computing for performance and energy improvement in multicore architectures, in ACM Great Lakes Symposium on VLSI (GLSVLSI), 2012
W. Wang, P. Mishra, Pre-DVS: preemptive dynamic voltage scaling for real-time systems with approximation scheme, in ACM/IEEE Design Automation Conference (DAC) (2010), pp. 705–710
W. Wang, P. Mishra, System-wide leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in multitasking systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (TVLSI) 20 (5), 902–910 (2012)
C.Y. Wang, K. Roy, Maximum power estimation for CMOS circuits using deterministic and statistical approaches. IEEE Trans. VLSI 6 (1), 134–140 (1998)
W. Wang, P. Mishra, S. Ranka, Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems, in ACM/IEEE Design Automation Conference (DAC) (2011), pp. 948–953
W. Wang, P. Mishra, S. Ranka, Dynamic Reconfiguration in Real-Time Systems - Energy, Performance, Reliability and Thermal Perspectives (Springer, New York, 2013). ISBN: 978-1-4614-0277-0
W. Wang, P. Mishra, A. Ross, Dynamic cache reconfiguration for soft real-time systems. ACM Trans. Embed. Comput. Syst. (TECS) 11 (2), article 28, 31 pp. (2012)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
Huang, Y., Mishra, P. (2017). Test Generation for Detection of Malicious Parametric Variations. In: Mishra, P., Bhunia, S., Tehranipoor, M. (eds) Hardware IP Security and Trust. Springer, Cham. https://doi.org/10.1007/978-3-319-49025-0_14
Download citation
DOI: https://doi.org/10.1007/978-3-319-49025-0_14
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-49024-3
Online ISBN: 978-3-319-49025-0
eBook Packages: EngineeringEngineering (R0)