Skip to main content
SpringerLink
Log in

State Space Obfuscation and Its Application in Hardware Intellectual Property Protection

  • Chapter
  • First Online:
Hardware Protection through Obfuscation

Abstract

In this chapter, we describe the methodology of state space obfuscation for sequential circuits and its application in hardware intellectual property (IP) protection against piracy and tampering attacks. The state space obfuscation is achieved by transforming a given hardware design through judicious modification of the state transition function and insertion of special logic structures at well-chosen locations inside a design. Such modifications perturb the circuit functionality to a maximum extent, while keeping the overall hardware and performance overheads low. Normal functionality is enabled by the application of a specific sequence of vectors at the circuit input, which acts as the enabling key for the circuit. The proposed state space obfuscation methodology effectively locks a gate-level design, and only a legitimate user can unlock it with the application of a predefined key in the form of a sequence of input vectors. We also extend the proposed obfuscation concept to make a given design more robust against hardware Trojan horse (HTH) insertion, thereby increasing the detectability of inserted HTH instances, while incurring low hardware and performance overheads. We present a suitable metric to quantify the level of obfuscation. Finally, we point toward extension of the concept for register transfer level (RTL ) circuit descriptions.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Castillo E, Meyer-Baese U, García A, Parrilla L, Lloris A (2007) IPP@HDL: efficient intellectual property protection scheme for IP cores. IEEE Trans VLSI 15:578–591

    Article  Google Scholar 

  2. Charbon E, Torunoglu I (2003) Watermarking techniques for electronic circuit design. In: IWDW’02: Proceedings of the international conference on digital watermarking, pp 147–169

    Google Scholar 

  3. Kahng A, Lach J, Mangione-Smith W, Mantik S, Markov I, Potkonjak M, Tucker P, Wang H, Wolfe G (2001) Constraint-based watermarking techniques for design IP protection. IEEE Trans CAD 20(10):1236–1252

    Article  Google Scholar 

  4. Lach J, Mangione-Smith W, Potkonjak M (1999) Robust FPGA intellectual property protection through multiple small watermarks. Proceedings of the 36th annual ACM/IEEE design automation conference, DAC’99. ACM, New York, pp 831–836

    Google Scholar 

  5. Oliveira A (2001) Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Trans CAD 20(9):1101–1117

    Article  Google Scholar 

  6. Chakraborty RS, Bhunia S (2009) HARPOON: a SoC design methodology for hardware protection through netlist level obfuscation. IEEE Trans CAD 28(10):1493–1502

    Article  Google Scholar 

  7. Roy JA, Koushanfar F, Markov IL (2008) EPIC: ending piracy of integrated circuits. In: DATE’08: Proceedings of the conference on Design, automation and test in Europe, pp 1069–1074

    Google Scholar 

  8. Adee S (2008) The hunt for the kill switch. IEEE Spectr 45(5):34–39

    Article  Google Scholar 

  9. Australian Government DoD-DSTO: Towards countering the rise of the silicon trojan (2008). http://dspace.dsto.defence.gov.au/dspace/bitstream/1947/9736/1/DSTO-TR-2220%20PR.pdf

  10. Defense Science Board: Task force on high performance microchip supply (2005). http://www.acq.osd.mil/dsb/reports/200502HPMSReportFinal.pdf

  11. King ST, Tucek J, Cozzie A, Grier C, Jiang W, Zhou Y (2008) Designing and implementing malicious hardware. In: LEET’08: Proceedings of the Usenix workshop on large-scale exploits and emergent threats, pp 5:1–5:8

    Google Scholar 

  12. DARPA: TRUST in Integrated Circuits (TIC) - Proposer Information Pamphlet (2007). http://www.darpa.mil/MTO/solicitations/baa07-24/index.html

  13. Wolff F, Papachristou C, Bhunia S, Chakraborty RS (2008) Towards Trojan-free trusted ICs: problem analysis and detection scheme,. In: DATE’08: Proceedings of the conference on design, automation and test in Europe, pp 1362–1365

    Google Scholar 

  14. Chakraborty RS, Wolff F, Paul S, Papachristou C, Bhunia S (2009) MERO: a statistical approach for hardware Trojan detection using logic testing. In: Clavier C, Gaj K (eds) Cryptographic Hardware and Embedded Systems - CHES 2009, vol 5737. Lecture Notes on Computer ScienceSpringer, Heidelberg, pp 396–410

    Chapter  Google Scholar 

  15. Agrawal D, Baktir S, Karakoyunlu D, Rohatgi P, Sunar B (2007) Trojan detection using IC fingerprinting. In: SP’07: Proceedings of the IEEE symposium on security and privacy, pp. 296–310

    Google Scholar 

  16. Jin Y, Makris Y (2008) Hardware Trojan detection using path delay fingerprint. In: HOST’08: Proceedings of the international workshop on hardware-oriented security and trust, pp 51–57

    Google Scholar 

  17. Narasimhan S, Du D, Chakraborty R, Paul S, Wolff F, Papachristou C, Roy K, Bhunia S (2010) Multiple-parameter side-channel analysis: a non-invasive hardware Trojan detection approach. In: HOST’10: Proceedings of the international workshop on hardware oriented security and trust, pp 13–18

    Google Scholar 

  18. Chinese firms favoring soft IP over hard cores (2011). http://www.eetasia.com/ART_8800440032_480100_NT_ac94df1c.HTM

  19. Wang C, Hill J, Knight JC, Davidson JW (2001) Protection of software-based survivability mechanisms. In: DSN’01: Proceedings of the international conference on dependable systems and networks, pp 193–202

    Google Scholar 

  20. ThicketTM family of source code obfuscators (2011). http://www.semdesigns.com

  21. Methodology for protection and licensing of HDL IP (2011). http://www.us.design-reuse.com/news/?id=12745&print=yes

  22. Brzozowski M, Yarmolik VN (2007) Obfuscation as intellectual rights protection in VHDL language. Proceedings of the 6th international conference on computer information systems and industrial management applications. IEEE Computer Society, Washington, DC, pp 337–340

    Google Scholar 

  23. Wirthlin MJ, McMurtrey B (2002) IP delivery for FPGAs using applets and JHDL. Proceedings of the 39th annual design automation conference, DAC’02. ACM, New York, pp 2–7

    Google Scholar 

  24. Hou T, Chen H, Tsai M (2006) Three control flow obfuscation methods for Java software. IEE Proc Softw 153(2):80–86

    Article  Google Scholar 

  25. Huang YL, Ho F, Tsai H, Kao H (2006) A control flow obfuscation method to discourage malicious tampering of software codes. In: ASIACCS’06: Proceedings of the 2006 ACM symposium on information, computer and communications security, pp 362–362

    Google Scholar 

  26. Linn C, Debray S (2003) Obfuscation of executable code to improve resistance to static disassembly. In: Proceedings of the ACM conference on computer and communications security, pp 290–299

    Google Scholar 

  27. Zhuang X, Zhang T, Lee H, Pande S (2004) Hardware assisted control flow obfuscation for embedded processors. In: CASES’04: Proceedings of the 2004 international conference on compilers, architecture, and synthesis for embedded systems, pp 292–302

    Google Scholar 

  28. Obfuscation by code morphing (2011). http://en.wikipedia.org/wiki/Obfuscated_code#Obfuscation_by_code_morphing

  29. Joepgen H, Krauss S (1993) Software by means of the protprog method. Elecktronik 42:52–56

    Google Scholar 

  30. Aucsmith D (1996) Tamper resistant software: an implementation. In: IH’96: Proceedings of the international workshop on information hiding, pp. 317–333

    Google Scholar 

  31. Schulman A (1993) Examining the windows AARD detection code. Dr. Dobb’s J 18 (1993)

    Google Scholar 

  32. Jakubowski M, Saw C, Venkatesan R (2009) Tamper-tolerant software: modeling and implementation. In: IWSEC’09: Proceedings of the international workshop on security: advances in information and computer security, pp 125–139

    Google Scholar 

  33. Chang H, Atallah M (2002) Protecting software code by guards. In: DRM’01: Revised papers from the ACM CCS-8 workshop on security and privacy in digital rights management, pp 160–175

    Google Scholar 

  34. Barak B, Goldreich O, Impagliazzo R, Rudich S, Sahai A, Vadhan S, Yang K (2001) On the (im)possibility of obfuscating programs. In: CRYPTO’01: Proceedings of the international cryptology conference on advances in cryptology, pp 1–18

    Google Scholar 

  35. Chakraborty RS, Bhunia S (2009) Hardware protection and authentication through netlist level obfuscation. In: ICCAD’08: Proceedings of the IEEE/ACM international conference on computer-aided design, pp 674–677

    Google Scholar 

  36. Wang F (2004) Formal verification of timed systems. Proc IEEE 92(8):1283–1305

    Article  Google Scholar 

  37. Alkabani YM, Koushanfar F, Potkonjak M (2007) Remote activation of ICs for piracy prevention and digital right management. In: ICCAD’07: Proceedings of the international conference on CAD, pp. 674–677

    Google Scholar 

  38. Moore WA, Kayfes PA (2007) US Patent 7213142 - system and method to initialize registers with an EEPROM stored boot sequence. http://www.patentstorm.us/patents/7213142/description.html

  39. The ISCAS-89 Benchmark Circuits. http://www.fm.vslib.cz/~kes/asic/iscas/

  40. Banga M, Hsiao MS (2008) A region based approach for the identification of hardware Trojans. In: HOST’08: Proceedings of the IEEE international workshop on hardware-oriented security and trust, pp 40–47

    Google Scholar 

  41. Alkabani YM, Koushanfar F (2007) Active hardware metering for intellectual property protection and security. In: SS’07: Proceedings of USENIX security symposium, pp. 20:1–20:16

    Google Scholar 

  42. Oliveira A (1999) Robust techniques for watermarking sequential circuit designs. In: DAC’99: Proceedings of the ACM/IEEE design automation conference, pp 837–842

    Google Scholar 

  43. Torunoglu I, Charbon E (2000) Watermarking-based copyright protection of sequential functions. IEEE J Solid-State Circ 35(3):434–440

    Article  Google Scholar 

  44. Yuan L, Qu G (2004) Information hiding in finite state machine. In: IH’04: Proceedings of the international conference on information hiding, IH’04, pp 340–354

    Google Scholar 

  45. Najm FN (1993) Transition density: a new measure of activity in digital circuits. IEEE Trans CAD 14(2):310–323

    Article  Google Scholar 

  46. Chou T, Roy K (1996) Accurate power estimation of CMOS sequential circuits. IEEE Trans VLSI 4(3):369–380

    Article  Google Scholar 

  47. Yotsuyanagi H, Kinoshita K (1998) Undetectable fault removal of sequential circuits based on unreachable states. In: VTS’98: Proceedings of the IEEE VLSI test symposium, pp 176–181

    Google Scholar 

  48. Koushanfar F (2012) Provably secure active IC metering techniques for piracy avoidance and digital rights management. IEEE Trans Inf Forensics Secur 7(1):51–63

    Article  Google Scholar 

  49. Lynn B, Prabhakaran M, Sahai A (2004) Positive results and techniques for obfuscation. Cryptology ePrint Archive, Report 2004/060. http://eprint.iacr.org/

  50. Chakraborty RS, Bhunia S (2009) Security against hardware Trojan through a novel application of design obfuscation. In: ICCAD’09: Proceedings of the international conference on CAD, pp 113–116

    Google Scholar 

  51. Roy JA, Kaushanfar F, Markov IL (2008) Extended abstract: circuit CAD tools as a security threat. In: HOST’08: Proceedings of the international workshop on hardware-oriented security and trust, pp 61–62

    Google Scholar 

  52. Systems, I.: Concorde – fast synthesis (2009). http://www.interrasystems.com/eda/eda_concorde.php

  53. Chakraborty R, Bhunia S (2009) Security through obscurity: an approach for protecting Register transfer level hardware IP. In: HOST’08: Proceedings of the international workshop on hardware oriented security and trust, pp 96–99

    Google Scholar 

  54. Chakraborty R, Bhunia S (2010) RTL hardware IP protection using key-based control and data flow obfuscation. In: VLSID’10: Proceedings of the international conference on VLSI Design, pp 405–410

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721302, West Bengal, India

    Rajat Subhra Chakraborty

  2. Department of Electrical and Computer Engineering, University of Florida, 336A Larsen Hall, Gainesville, Florida, 32611-6200, USA

    Swarup Bhunia

Authors
  1. Rajat Subhra Chakraborty
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Swarup Bhunia
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Rajat Subhra Chakraborty .

Editor information

Editors and Affiliations

  1. University of Florida, Gainseville, Florida, USA

    Domenic Forte

  2. University of Florida, Gainseville, Florida, USA

    Swarup Bhunia

  3. University of Florida, Gainseville, Florida, USA

    Mark M. Tehranipoor

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this chapter

Cite this chapter

Chakraborty, R.S., Bhunia, S. (2017). State Space Obfuscation and Its Application in Hardware Intellectual Property Protection. In: Forte, D., Bhunia, S., Tehranipoor, M. (eds) Hardware Protection through Obfuscation. Springer, Cham. https://doi.org/10.1007/978-3-319-49019-9_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-49019-9_8

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-49018-2

  • Online ISBN: 978-3-319-49019-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation