Abstract
Tables 6.1, 6.3, and 6.4 present the results of our lifetime evaluation scheme for the set of library cells considering the output, Vdd, and Vss pin placement, respectively, at 2 GHz. The best and worst TTF values correspond to the largest and smallest lifetimes over all pin candidates. The TTF is calculated for two different switching activities (α) of 50 and 100 % of the clock frequency: although few cells in a layout switch frequently, it is likely one of these cells that could be an EM bottleneck. The 100 % switching case is a clear upper bound on the lifetime of the cell: typical cells, even worst-case cells, switch at a significantly lower rate, except on always-on networks such as core elements of the clock network. The tables show that the pin position is important: choosing a good pin position could better balance current flow and improve EM lifetime. It can be noted that the worst TTFs for the X16 cells are extremely small: this is due to the large number of pin choices for such cells, and due to the effects of large currents associated with specific pin positions, as well as divergence effects.
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Posser, G., Sapatnekar, S.S., Reis, R. (2017). Results. In: Electromigration Inside Logic Cells. Springer, Cham. https://doi.org/10.1007/978-3-319-48899-8_6
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DOI: https://doi.org/10.1007/978-3-319-48899-8_6
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