Skip to main content

State of the Art

  • Chapter
  • First Online:
Electromigration Inside Logic Cells

Abstract

EM is a well-known problem and many methods have been proposed to model and to mitigate the EM effects in different design stages, as Sect. 2.1 presents, for different types of interconnections as presented in Sect. 2.2.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Ampacity is the maximum amount of electrical current a conductor or device can carry before sustaining immediate or progressive deterioration.

References

  • Abella J, Vera X, Unsal O, Ergin O, Gonzalez A, Tschanz J (2008) Refueling: preventing wire degradation due to electromigration. IEEE Micro 28(6):37–46

    Article  Google Scholar 

  • Balhiser D, Gentry J, Harber R, Haskin B, Marcoux P, Stong G (2005) Process and system for identifying wires at risk of electromigration. US Patent App. 10/241,623. http://www.google.com.br/patents/US20040049750

  • Barwin J, Bickford J (2013) Method of managing electro migration in logic designs and design structure thereof. US Patent 8,560,990. http://www.google.com/patents/US8560990

  • Barwin J, Chung J, Joshi A, Livingstone W, Sigal L, Worth B, Zuchowski P (2015) Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design. US Patent 9,104,832. https://www.google.com/patents/US9104832

  • Butzen PF (2012) Aging aware design techniques and CMOS gate degradation estimative. Ph.D. thesis (doctorate in microelectronics), Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS - Brazil

    Google Scholar 

  • Cadence (2013) Cadence SOC encounter user guide. Available at: http://www.cadence.com/products/di/first_encounter/pages/default.aspx. Visited on: Jul 2013

  • Cadence (2016) Cadence virtuoso liberate characterization solution. Available at: https://www.cadence.com/content/cadence-www/global/en_US/home/tools/custom-ic-analog-rf-design/library-characterization/virtuoso-liberate-characterization.html

  • Chatterjee S, Fawaz M, Najm FN (2013) Redundancy-aware electromigration checking for mesh power grids. In: IEEE/ACM international conference on computer-aided design, ICCAD 2013. IEEE Press, Piscataway, NJ, pp 540–547

    Google Scholar 

  • Chen W (1999) The VLSI handbook. Electrical engineering handbook. Taylor and Francis, New York. http://books.google.com.br/books?id=0r5LihlMogkC

  • Cheng Y, Todri-Sanial A, Bosio A, Dillio L, Girard P, Virazel A, Vevet P, Belleville M (2013) A novel method to mitigate tsv electromigration for 3d ics. In: IEEE computer society annual symposium on VLSI, ISVLSI 2013, pp 121–126. doi:10.1109/ISVLSI.2013.6654633

  • Choi ZS, Gan C, Wei F, Thompson CV, Lee J, Pey K, Choi W (2004) Fatal void size comparisons in via-below and via-above cu dual-damascene interconnects. In: MRS proceedings materials, technology and reliability of advanced interconnects, vol 812. Cambridge University Press, Cambridge, pp F7–6. doi:http://dx.doi.org/10.1557/PROC-812-F7.6

  • Domae S, Ueda T (2001) CMOS inverter and standard cell using the same. US Patent 6,252,427

    Google Scholar 

  • Fawaz M, Chatterjee S, Najm FN (2013) A vectorless framework for power grid electromigration checking. In: International conference on computer-aided design, ICCAD 2013. IEEE Press, Piscataway, NJ, pp 553–560

    Google Scholar 

  • Flach G, Reimann T, Posser G, Johann M, Reis R (2013) Simultaneous gate sizing and Vth assignment using lagrangian relaxation and delay sensitivities. In: IEEE computer society annual symposium on VLSI, ISVLSI 2013, IEEE, pp 84–89

    Google Scholar 

  • Flach G, Reimann T, Posser G, Johann M, Reis R (2014) Effective method for simultaneous gate sizing and Vth assignment using lagrangian relaxation. IEEE Trans Comput Aided Des Integr Circuits Syst 33(4):546–557. doi:10.1109/TCAD.2014.2305847

    Article  Google Scholar 

  • Jain P, Jain A (2012) Accurate current estimation for interconnect reliability analysis. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(9):1634–1644

    Article  Google Scholar 

  • Jain P, Cortadella J, Sapatnekar SS (2016) A fast and retargetable framework for logic-ip-internal electromigration assessment comprehending advanced waveform effects. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(6):2345–2358. doi:10.1109/TVLSI.2015.2505504

    Article  Google Scholar 

  • Jerke G, Lienig J (2010) Early-stage determination of current-density criticality in interconnects. In: 11th international symposium on quality electronic design, ISQED 2010, pp 667–674. doi:10.1109/ISQED.2010.5450505

    Google Scholar 

  • Kahng A (2011) VLSI physical design: from graph partitioning to timing closure. Springer Science and Business Media, New York. http://books.google.com.br/books?id=DWUGHyFVpboC

    Book  MATH  Google Scholar 

  • Kahng A, Nath S, Rosing T (2013a) On potential design impacts of electromigration awareness. In: 18th Asia and South Pacific design automation conference, (ASP-DAC) 2013, pp 527–532. doi:10.1109/ASPDAC.2013.6509650

  • Kahng AB, Kang S, Lee H (2013b) Smart non-default routing for clock power reduction. In: 50th annual design automation conference, DAC 2013. ACM, New York, pp 91:1–91:7. doi:10.1145/2463209.2488846. http://doi.acm.org/10.1145/2463209.2488846

  • Lee JH (2012a) Implications of modern semiconductor technologies on gate sizing. PhD thesis, University of California, Los Angeles

    Google Scholar 

  • Li B, Gill J, Christiansen C, Sullivan T, McLaughlin PS (2005) Impact of via-line contact on Cu interconnect Electromigration performance. In: IEEE international reliability physics symposium, IRPS 2005, pp 24–30. doi:10.1109/RELPHY.2005.1493056

  • Li B, Christiansen C, Badami D, Yang CC (2014) Electromigration challenges for advanced on-chip cu interconnects. Microelectron Reliab 54(4):712–724. doi:http://dx.doi.org/10.1016/j.microrel.2014.01.005. http://www.sciencedirect.com/science/article/pii/S0026271414000092

  • Li DA, Marek-Sadowska M, Nassif SR (2015b) T-vema: A temperature- and variation-aware electromigration power grid analysis tool. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(10):2327–2331. doi:10.1109/TVLSI.2014.2358678

  • Lienig J (2006) Introduction to electromigration-aware physical design. In: International symposium on physical design, ISPD 2006. ACM, New York, pp 39–46. doi:10.1145/1123008.1123017. http://doi.acm.org/10.1145/1123008.1123017

  • Lienig J (2013) Electromigration and its impact on physical design in future technologies. In: ACM international symposium on physical design, ISPD 2013, pp 33–40

    Google Scholar 

  • Mishra V, Sapatnekar S (2013) The impact of electromigration in copper interconnects on power grid integrity. In: 50th ACM/IEEE design automation conference, DAC 2013, pp 1–6

    Google Scholar 

  • Mishra V, Sapatnekar SS (2015) Circuit delay variability due to wire resistance evolution under ac electromigration. In: 2015 IEEE international reliability physics symposium, pp 3D.3.1–3D.3.7. doi:10.1109/IRPS.2015.7112713

  • Mishra V, Sapatnekar SS (2016) Predicting electromigration mortality under temperature and product lifetime specifications. In: Proceedings of the 53rd annual design automation conference, DAC ’16. ACM, New York, pp 43:1–43:6. doi:10.1145/2897937.2898070. http://doi.acm.org/10.1145/2897937.2898070

  • Nguyen H, Salm C, Wenzel R, Mouthaan A, Kuper F (2002) Simulation and experimental characterization of reservoir and via layout effects on electromigration lifetime. Microelectron Reliab 42(9–11):1421–1425. http://doc.utwente.nl/67753/

    Article  Google Scholar 

  • Pak J, Lim SK, Pan DZ (2013) Electromigration study for multi-scale power/ground vias in tsv-based 3d ics. In: International conference on computer-aided design, ICCAD 2013. IEEE Press, Piscataway, NJ, pp 379–386

    Google Scholar 

  • Park YJ, Jain P, Krishnan S (2010) New electromigration validation: via node vector method. In: International reliability physics symposium, IRPS 2010, pp 698–704

    Google Scholar 

  • Posser G, Flach G, Wilke G, Reis R (2012) Gate sizing using geometric programming. Analog Integr Circuits Sig Process 73(3):831–840

    Article  Google Scholar 

  • Posser G, Belomo J, Meinhardt C, Reis R (2014a) Perfomance improvement with dedicated transistor sizing for mosfet and finfet devices. In: IEEE computer society annual symposium on VLSI, ISVLSI 2014, IEEE, pp 418–423

    Google Scholar 

  • Pullela S, Menezes N, Pillage L (1995) Low power ic clock tree design. In: IEEE custom integrated circuits conference, CICC 1995, pp 263–266. doi:10.1109/CICC.1995.518182

  • Rabaey JM, Chandrakasan AP, Nikolic B (2002) Digital integrated circuits. Prentice Hall, Englewood Cliffs

    Google Scholar 

  • Reimann T, Posser G, Flach G, Johann M, Reis R (2013) Simultaneous gate sizing and Vt assignment using fanin/fanout ratio and Simulated Annealing. In: IEEE international symposium on circuits and systems, ISCAS 2013, IEEE, pp 2549–2552

    Google Scholar 

  • SI2 (2009) LEF DEF guide. Available at: http://www.si2.org/openeda.si2.org/projects/lefdef. Visited on: Apr 2013

  • Skadron K, Stan M, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D (2003) Temperature-aware microarchitecture. In: 30th annual international symposium on computer architecture, ISCA 2003, pp 2–13. doi:10.1109/ISCA.2003.1206984

    Google Scholar 

  • Summers K (2013) Five-minute tutorial: creating an em model file. Available at: http://www.cadence.com/Community/blogs/di/archive/2013/01/14/five-minute-tutorial-creating-an-em-model-file.aspx. Visited on: Jan 2014

  • Synopsys (2013b) Synopsys design compiler user guide. Available at: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/DCUltra/pages/default.aspx. Visited on: Jun 2013

  • Synopsys (2014a) Ic compiler: comprehensive place and route system. http://www.synopsys.com/Tools/Implementation/PhysicalImplementation/Documents/iccompiler_ds.pdf. Visited on: May 2013

  • Synopsys (2014b) Synopsys 32/28nm open pdk. Available at: http://www.synopsys.com. Visited on: Mar 2014

  • Synopsys (2016) Synopsys siliconsmart. Available at: http://www.synopsys.com/Tools/Implementation/SignOff/Pages/siliconsmart-ds.aspx.

  • Thompson C (2008) Using line-length effects to optimize circuit-level reliability. In: 15th international symposium on the physical and failure analysis of integrated circuits, 2008. IPFA 2008, IEEE, pp 1–4

    Google Scholar 

  • Tu KN (2003) Recent advances on electromigration in very-large-scale-integration of interconnects. J Appl Phys 94(9):5451–5473. doi:http://dx.doi.org/10.1063/1.1611263. http://scitation.aip.org/content/aip/journal/jap/94/9/10.1063/1.1611263

  • Weste NHE, Harris D (2005) CMOS VLSI design: a circuits and systems perspective. Addison-Wesley Publishing Company, Boston

    Google Scholar 

  • White D, McSherry M, Fischer E, Yanagida B, Gopalakrishnan P (2016) Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. US Patent 9,330,222. https://www.google.com/patents/US9330222

  • Xie J, Narayanan V, Xie Y (2012) Mitigating electromigration of power supply networks using bidirectional current stress. In: Great lakes symposium on VLSI, GLSVLSI 2012, pp 299–302

    Google Scholar 

  • Zhao X, Wan Y, Scheuermann M, Lim SK (2013) Transient modeling of tsv-wire electromigration and lifetime analysis of power distribution network for 3d ICS. In: International conference on computer-aided design, ICCAD 2013. IEEE Press, Piscataway, NJ, pp 363–370

    Google Scholar 

  • Zhou C, Wang X, Fung R, Wen SJ, Wong R, Kim CH (2015) High frequency AC electromigration lifetime measurements from a 32nm test chip. In: 2015 symposium on VLSI technology (VLSI technology), pp T42–T43. doi:10.1109/VLSIT.2015.7223696

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this chapter

Cite this chapter

Posser, G., Sapatnekar, S.S., Reis, R. (2017). State of the Art. In: Electromigration Inside Logic Cells. Springer, Cham. https://doi.org/10.1007/978-3-319-48899-8_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-48899-8_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-48898-1

  • Online ISBN: 978-3-319-48899-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics