Abstract
Emerging memories currently in development in the electronics industry have in common the fact that the signal to be detected is a change of electrical resistance of the memory material, even though the way in which this resistance variation is obtained is different for each of the technologies considered.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
“Circuit Design in Emerging Technologies” TD forum, ISSCC 2006
“Non-Volatile Memories Technology and Design”, Memory Design Forum, ISSCC 2004
“Non volatile memory circuit, design and technology” Short course F1, ISSCC 2007
G. Campardo et al. “An Overview of Flash Architectural Developments” Proceeding of the IEEE, April 2003
R. Micheloni et al. “The Flash Memory Read Path: building blocks and critical aspects” Proceeding of the IEEE, April 2003
G. Campardo et al. “VLSI-Design of Non-Volatile Memories”, Springer Series in Advanced Microelectronics, 2005.
“DRAM’s in the 21st Century” IEDM1996 short course, organizer: S. Shinozaki
“Advanced Dynamic Memory Design” Memory Design Forum, ISSCC 2005
G. Campardo et al. “Architecture of non volatile memory with multi-bit cells” Elsevier Science, Microelectronic Engineering, Volume 59, Issue 1–4, November 2001, pp. 173–181
G. Casagrande “Phase Change Memory” Tutorial, ISSCC 2004
H. Chung et al. “A 58 nm 1.8 V 1 Gb PRAM with 6.4 MB/s Program BW” ISSCC 2011, Digest of technical papers
C. Villa et al. “a 45 nm 1 Gb 1.8 V phase-change memory” ISSCC2010, Digest of technical papers
Y. Choi et al “A 20 nm 1.8 V 8 Gb PRAM with 40 MB/s Program bandwidth” ISSCC2012, Digest of technical papers
S. Hollmer “A CMOS Compatible Embedded 1 Mb CBRAM NVM” ISSCC 2012, Digest of technical papers
W. Otsuka “A 4 Mb Conductive Bridge Resistive Memory with 2.3 GB/s Read-throughput and 216 MB/s Program throughput” ISSCC2011, Digest of technical papers
R. Fackenthal et al. “A 16 Gb Re-RAM with 600 MB/s write and 1 GB/s read in 27 nm technology” ISSCC2014, Digest of technical papers
F. Bedeschi et al. “A multilevel cell bipolar selected Phase Change memory” ISSCC2008, Digest of technical papers
T. Kawahara et al. “Spin-transfer torque RAM technology: review and prospect” Microelectronic reliability 52 (2012), pp. 613–627
D. Halupka et al. “Negative resistance Read&Write schemes for STT-MRAM in 0.13 um CMOS” ISSCC 2010 Digest of technical papers
G. Jeong et al. “A 0.24-μm 2.0 V 1T1MTJ 16 Kb non-volatile magnetoresistance RAM with self-reference scheme” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1906–1910, Nov. 2003
Z. Sun et al. “Voltage driven Non Destructive Self-Reference Sensing Scheme of Spin Transfer Torque Memory” IEEE trans. on VLSI Systems vol. 20, no. 11, Nov. 2012
R. Takemura et al. “highly scalable Disruptive Reading scheme for Gb-scale SPRAM and beyond” ISSCC2010, Digest of technical papers
A. Sheikholeslami et al. “A survey of Circuit Innovation in Ferroelectric Random-access Memories” Proc. of the IEEE, vol. 88, no. 5, May 2000
A.G. Papaliolios “Dynamic Adjusting Reference Voltage for Ferroelectric Circuits” U.S. Patent 5218566, June 8, 1993
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
Gastaldi, R. (2017). Data Sensing in Emerging NVMs. In: Gastaldi, R., Campardo, G. (eds) In Search of the Next Memory. Springer, Cham. https://doi.org/10.1007/978-3-319-47724-4_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-47724-4_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-47722-0
Online ISBN: 978-3-319-47724-4
eBook Packages: EngineeringEngineering (R0)