Divergence Detection for CCSL Specification via Clock Causality Chain

  • Qingguo XuEmail author
  • Robert de Simone
  • Julien DeAntoni
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9984)


The Clock Constraint Specification Language (CCSL), first introduced as a companion language for Modeling and Analysis of Real-Time and Embedded systems (MARTE), has now evolved beyond the time specification of MARTE, and has become a full-fledged domain specific modeling language widely used in many domains. A CCSL specification is a set of constraints, which symbolically represents a set of valid clock schedules, where a schedule represents the order of the actions in a system. This paper proposes an algorithm to detect the divergence behavior in the schedules that satisfy a given CCSL specification (i.e. it proposes to detect the presence of infinite but non periodic schedules in a CCSL specification). We investigate the divergence by constructing causality chains among the clocks resulting from the constraints of the specification. Depending on cycles in the causality chains, a bounded clock set built by our proposed algorithm can be used to decide whether the given specification is divergence-freedom or not. The approach is illustrated on one example for architecture-driven analysis.


CCSL Divergence Clock causality chain Bounded Clock Set PVS 


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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Qingguo Xu
    • 1
    • 2
    Email author
  • Robert de Simone
    • 3
  • Julien DeAntoni
    • 3
  1. 1.School of Computer Engineering and ScienceShanghai UniversityShanghaiChina
  2. 2.Shanghai Key Laboratory of Computer Software Testing and EvaluatingShanghaiChina
  3. 3.Inria Sophia Antipolis Méditerranée AOSTE, University of Nice Sophia Antipolis, I3SSophia Antipolis CedexFrance

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