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Very Large Scale Integration (VLSI) and ASICs

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Abstract

The continuing development of IC technology during the last couple of decades has led to a considerable increase in the number of devices per unit chip area. The resulting feasible IC complexity currently allows the integration of a complete system on a chip (SOC) , which may comprise hundreds of millions to a few billion transistors.

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References

  1. A. Abbo et al., XETAL-II: A 107 GOPS, 600 mW massively-parallel processor for video scene analysis. ISSCC Digest of Technical Papers, San Francisco, 2007

    Google Scholar 

  2. R. Goering, Startup Liga promises to rev simulation, EE Times, 17 July 2006

    Google Scholar 

  3. P. Coussy et al., An introduction to high-level synthesis. IEEE Des. Test Comput. 26 (4), 8–17 (2009)

    Article  Google Scholar 

  4. E. Oruklu et al., System-on-chip design using high-level synthesis tools. Circuits Syst. 3, 1–9 (2012)

    Article  Google Scholar 

  5. K. Karras et al., High-level synthesis case study:implementation of a memcached server, in 1st International Workshop on FPGAs for Software Programmers (FSP 2014), Munich, Germany, 1 September 2014

    Google Scholar 

  6. S. Sikand, IP Reuse – Design and Verification Report 2013, IC Manage Inc., 2016

    Google Scholar 

  7. C. Forzana, D. Pandini, Statistical static timing analysis: a survey. Integr. VLSI J. 42, 409–435 (2009). Elsevier, 2009

    Google Scholar 

  8. S.J. Wan et al., Fast and accurate statistical static timing analysis, in IEEE International Symposium on Circuits and Systems (ISCAS), 2014

    Google Scholar 

  9. A.M. Baker, Y. Jiang, Modeling and architectural simulations of the statistical static timing analysis of the non-gaussian variation sources for VLSI circuits, in International Journal of Scientific and Research Publications, vol. 3, issue 1 (Trans Tech Publications, Durnten-Zurich, 2013)

    Google Scholar 

  10. A. Malik et al., VLSI: techniques for efficient standard cell placement, in IJSE-ITS: Race-2014 (2014). ISSN:2347-2200/V2-N1/PP-17-21

    Google Scholar 

  11. A. Hassan, Fundamentals of Floor Planning A Complex SoC. Electronic Design, 21 Mar 2012

    Google Scholar 

  12. I. Okhura, et al., A novel basic cell configuration for CMOS gate-array, in Custom Intergrated Circuits Conference 1982, pp 307–310, May 1982

    Google Scholar 

  13. H.J.M. Veendrick et al., An efficient and flexible architecture for high-density gate arrays. ISSCC Digest of Technical Papers, San Francisco, 1990

    Book  Google Scholar 

  14. Z. Or-Bach, FPGAs as ASIC alternatives: Past and Future. EE Times, 21 Apr 2014

    Google Scholar 

  15. See current CPLD architectures on the CPLD vendors websites: Altera, Xilinx, Lattice, Cypres, etc., 2016

    Google Scholar 

  16. Structured Arrays/Gate Arrays; FFSA/Fit FAST Structured ARRAY (2014), http://toshiba.semicon-storage.com/eu/product/asic/structured-arrays.html

  17. M. Maxfield, Is it an ASIC? Is it an FPGA? No, itś eASIC!. EE Times, 14 Sept 2015

    Google Scholar 

  18. H. de Man et al., An intelligent module generator environment, in Proceedings of the 23rd Design Automation Conference, pp. 730–735 (1986)

    Google Scholar 

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J.M. Veendrick, H. (2017). Very Large Scale Integration (VLSI) and ASICs. In: Nanometer CMOS ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-47597-4_7

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  • DOI: https://doi.org/10.1007/978-3-319-47597-4_7

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-47595-0

  • Online ISBN: 978-3-319-47597-4

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