Abstract
The prolonged scaling of CMOS devices according to Moore’s law, has brought the design complexity in terms of number of transistors and performance requirements to such a high level, that design styles and methods continuously need to be changed in order to manage this complexity and to enable full exploitation of the potentials of advanced and future CMOS technologies. A prediction of these potentials was presented in the International Technology Roadmap for Semiconductors (ITRS) [1], launched in 1991 by the Semiconductor Industrial Association (SIA) . Traditionally, this ITRS roadmap was updated every 2 years. Because the semiconductor industry is rapidly approaching a brick wall, leaving only a few players who can afford the huge investments needed for further scaling, the continuation of the ITRS roadmap has become questionable. The ITRS 2013 roadmap is probably the last version.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Semiconductors Industrial Associations, ITRS roadmap, 2013 update, http://www.itrs.net
M. Vertregt et al., Scalable high-speed analog circuit design, in 2001 American Academy of Cosmetic Dentistry (Kluwer Academic Publishers, Boston, 2002), pp 3–21
M. Izumikawa et al., A 0.25 μm 0.9 V 100 MHz DSP core. IEEE J. Solid-State 32 (1), 52–61 (1997)
T. Kuroda et al., A 0.9 V, 150 MHz, 10 mW, 4 mm2, 2-D DCT core processor with variable threshold voltage scheme. IEEE J. Solid-State Circuits 1770–1779 (1996)
S.H. Lo et al., Quantum-Mechanical modelling of electron tunnelling current from the inversion layer of ultra-thin-oxide in MOSFET’s. IEEE Electron Device Lett. 18 (5), 209–211 (1997)
B. Johnson et al., Market trends: rising costs of production limit availability of leading-edge Fabs’, Gartner Report, 17 Sept 2012
J. Ribeiro, Samsung investing $14.7 billion in new chip fabrication facility. IDG News Service, 6 Oct 2014
H. Jones, Why migration to 20 nm bulk CMOS and 16/14 nm FinFETs is not a best approach for semiconductor industry, White Paper, International Business Strategies, Inc., January 2014
C. Piguet, Microelectronics for systems-on-chips, in Coursebooks CSEM, Neuchâtel, Switzerland, 2015/2016
F. von Trapp, Executive interview: bill bottoms talks about revamping the ITRS roadmap, 12 Mar 2015, http://www.3dincites.com/2015/03/executive-interview-bill-bottoms-talks-revamping-itrs-roadmap/
E. Korczynski, 3D-NAND deposition and etch integration, in Semiconductor Manufacturing and Design Community, Sept 2016, http://semimd.com/blog/tag/3d-nand/
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
J.M. Veendrick, H. (2017). Effects of Scaling on MOS IC Design and Consequences for the Roadmap. In: Nanometer CMOS ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-47597-4_11
Download citation
DOI: https://doi.org/10.1007/978-3-319-47597-4_11
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-47595-0
Online ISBN: 978-3-319-47597-4
eBook Packages: EngineeringEngineering (R0)