Abstract
Distributed real-time systems are notoriously difficult to design, and must be verified, e. g., using model checking. In particular, deadlocks must be avoided as they either yield a system subject to potential blocking, or denote an ill-formed model. Timed automata are a powerful formalism to model and verify distributed systems with timing constraints. In this work, we investigate synthesis of timing constants in timed automata for which the model is guaranteed to be deadlock-free.
This work is partially supported by the ANR national research program PACS (ANR-14-CE28-0002).
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Notes
- 1.
Experiments were conducted on Linux Mint 17 64 bits, running on a Dell Intel Core i7 CPU 2.67 GHz with 4 GiB. Binaries, models and results are available at www.imitator.fr/static/ICTAC16/.
- 2.
The synchronous product of several PTA components (using synchronized actions) yields a PTA. IMITATOR performs this composition on-the-fly.
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André, É. (2016). Parametric Deadlock-Freeness Checking Timed Automata. In: Sampaio, A., Wang, F. (eds) Theoretical Aspects of Computing – ICTAC 2016. ICTAC 2016. Lecture Notes in Computer Science(), vol 9965. Springer, Cham. https://doi.org/10.1007/978-3-319-46750-4_27
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