Introduction

Abstract

The increase in chip complexity over past few years has created the need to implement complete analog and digital subsystems on the same integrated circuit using the same technology. Figure 1.1 shows the roadmap for the technology scaling. The increase in demand for battery operated portable devices and implantable medical devices has placed added pressure on lowered supply voltages. Technology scaling reduces the delay of the circuit elements, enhancing the operating frequency of an integrated circuit. The density and number of transistors on an IC increases with the scaling of the feature sizes. Today we are at 14 nm FINFET technology. Reducing power dissipation has become an important objective in the design of digital circuits. One common technique for reducing power is to reduce the supply voltage. Reduction in supply voltage demands proportional scaling of threshold voltage to maintain the same ON current. However scaling of threshold voltage increases the sub threshold leakage or the OFF current. Hence threshold voltage does not scale proportional to the supply voltage. Technology scaling (Fig. 1.1) is a robust roadmap (www.itrs.net) for digital circuits, while analog circuits strongly suffer from this trend, and this is becoming a crucial bottle neck in the realization of a system on chip in a scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the supply voltage, and this limits the analog performance in qualitative (is it possible to operate from a low voltage?) and quantitative (if it is possible to operate, which performance is achievable?) terms [1].