Abstract
In this paper a hardware implementation in a field programmable gate array (FPGA) device of moving object segmentation using the flux tensor (FT) method is presented. The used algorithm and its parallelized version are described in details. The designed module has been verified on the VC 707 development board with Virtex 7 FPGA device for the following video stream parameters: \(720 \times 576\) @ 50 fps (25 MHz pixel clock), \(1280 \times 720\) @ 50 fps (74.25 MHz pixel clock) and \(1920 \times 1080\) @ 50 fps (148.5 MHz pixel clock). Additionally, the computing performance and power consumption have been estimated. The proposed module outperforms the previous FT implementations both in terms of real-time processing capabilities for high-definition stream, as well as energy efficiency.
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- 1.
720p denotes that the vertical resolution of the image equals 720 lines and progressive scanning is used (not interlacing). Usually 720p means a \(1280 \times 720\) resolution.
- 2.
Even if the available memory resources are greater than the required 47 Mb, combining many distributed across the FPGA device block RAM modules is very problematic and inefficient.
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The work presented in this paper was supported by AGH University of Science and Technology project number 15.11.120.879.
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Janus, P., Piszczek, K., Kryjak, T. (2016). FPGA Implementation of the Flux Tensor Moving Object Detection Method. In: Chmielewski, L., Datta, A., Kozera, R., Wojciechowski, K. (eds) Computer Vision and Graphics. ICCVG 2016. Lecture Notes in Computer Science(), vol 9972. Springer, Cham. https://doi.org/10.1007/978-3-319-46418-3_43
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