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Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures

  • Nalini KumarEmail author
  • Carlo Pascoe
  • Christopher Hajas
  • Herman Lam
  • Greg Stitt
  • Alan George
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9945)

Abstract

This paper presents a simulation methodology called Behavioral Emulation (BE) for scalable design-space exploration of algorithms and architectures. By design, BE is independent of simulation vehicle (e.g., simulation in software or emulation in hardware) and addresses system-simulation complexity with a coarse-grained, multi-scale approach. We describe the BE methodology, component models, and simulation workflow from calibration to validation of applications simulated on existing architectures and present a device-level case study with roughly 10 % relative error. Finally, we discuss the extension of validated models to predict application performance on notional architectures.

Keywords

Behavioral Emulation Performance modeling Coarse-grained simulation Design space exploration 

Notes

Acknowledgment

This work is supported by the U.S. Department of Energy, National Nuclear Security Administration, Advanced Simulation and Computing Program, as a Cooperative Agreement under the Predictive Science Academic Alliance Program, under Contract No. DE-NA0002378. This work was supported in part by the I/UCRC Program of the National Science Foundation under Grant Nos. EEC-0642422 and IIP-1161022.

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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Nalini Kumar
    • 1
    Email author
  • Carlo Pascoe
    • 1
  • Christopher Hajas
    • 1
  • Herman Lam
    • 1
  • Greg Stitt
    • 1
  • Alan George
    • 1
  1. 1.Department of ECE, PSAAP II Center for Compressible Multiphase Turbulence, NSF Center for High-Performance Reconfigurable ComputingUniversity of FloridaGainesvilleUSA

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