Abstract
The modelling techniques of the concurrent control systems in hardware description languages (HDLs) are presented in this chapter. Two modelling approaches are shown. The first one includes the traditional modelling concept of the concurrent system specified by an interpreted Petri net. The controller is simply described according to its behavior. Particular states (markings) of the system change due to the transitions firings. There is no decomposition nor division of the system into sub-modules. Therefore, there is no possibility of further partial reconfiguration of the prototyped controller. The second technique involves decomposition of the concurrent control system. Each of the achieved components is modelled separately as a sequential automaton (such as an FSM), however proper synchronization ought to be assured. The modular concept benefits in the possibility of the further partial reconfiguration (either static or dynamic) of the system (cf. Chap. 9).
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References
Adamski M, Wegrzyn M (2009) Petri nets mapping into reconfigurable logic controllers. Electron Telecommun Q 55(2):157–182
Barkalov A, Titarenko L (2009) Logic synthesis for FSM-based control units, vol 53. Lecture Notes in Electrical Engineering, Springer, Berlin
Bazydlo G, Adamski M (2011) Specification of UML 2.4 HSM and its computer based implementation by means of Verilog. Przeglad Elektrotechniczny 87(11):145–149 in Polish
Blunno I, Lavagno L (2000) Automated synthesis of micro-pipelines from behavioral verilog HDL. In: (ASYNC 2000) Proceedings of the sixth international symposium on advanced research in asynchronous circuits and systems, 2000, IEEE, pp 84–92
Brown S, Vernesic Z (2000) Fundamentals of digital logic with VHDL design. McGraw Hill, New York, USA
Bukowiec A, Tkacz J, Gratkowski T, Gidlewicz T (2013) Implementation of algorithm of Petri nets distributed synthesis into FPGA. Int J Electron Telecommun 59:317–324
Bukowiec A, Doligalski M (2013) Petri net dynamic partial reconfiguration in FPGA. In: Computer aided systems theory-EUROCAST, Springer, pp 436–443
Bukowiec A, Mróz P (2012) An FPGA synthesis of the distributed control systems designed with Petri nets. In: Proceedings of the IEEE 3rd international conference on networked embedded systems for every application, Liverpool, UK, pp 1–6
Czerwinski R, Kania D (2012) Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocess Microsyst—Embed Hardw Des 36(1):45–61
Gomes L, Costa A, Barros JP, Lima P (2007) From Petri net models to VHDL implementation of digital controllers. In: IECON 2007. 33rd annual conference of the IEEE industrial electronics society, 2007, IEEE, pp 94–99
Grobelna I (2013) Formal verification of logic controller specification by means of model checking. University of Zielona Góra Press
IEEE Standard for Verilog Hardware Description Language (2006)
Mallet F, Gaff\(\acute{e}\) D, Bo\(\acute{e}\)ri F (2000) Concurrent control systems: from grafcet to VHDL. In: EUROMICRO, IEEE Computer Society, pp 1230–1234
Minns P, Elliott I (2008) FSM-based digital design using Verilog HDL, Wiley
Moore E (1956) Gedanken experiments on sequential machines. In: Automata studies, PUP, pp 129–153
Palnitkar S (2003) Verilog HDL: a guide to digital design and synthesis, vol 1. Prentice Hall Professional
Sudacevschi V, Ababii V, Gutuleac E, Negura V (2010) HDL implementation from Petri nets description. In: 10th International conference on development and application systems, pp 236–240
Thomas D, Moorby P (2002) The verilog hardware description language, \(5^{th}\) edn. Kluwer Academic Publishers, Norwell, MA
Thomas D, Moorby P (2008) The Verilog hardware description language, Springer Science & Business Media
Vanbekbergen P, Wang A, Keutzer K (1995) A design and validation system for asynchronous circuits. In: Proceedings of the 32nd annual ACM/IEEE design automation conference, ACM, pp 725–730
Wegrzyn M (2006) Petri net decomposition approach for partial reconfiguration of logic controllers. In: Proceedings of the workshop on discrete-event system design, Rydzyna, Poland, pp 323–328
Wiśniewski R (2009) Synthesis of compositional microprogram control units for programmable devices, vol 14. Lecture Notes in Control and Computer ScienceUniversity of Zielona Góra Press, Zielona Góra
Xilinx primitives (Virtex-5 family). http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_scm.pdf. Accessed 04 March 2016
Yakovlev A, Gomes L, Lavagno L (2000) Hardware design and Petri nets, Springer
Zwolinski M (2000) Digital system design with VHDL. Addison-Wesley Longman Publishing Co. Inc, Boston, MA, USA
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Wiśniewski, R. (2017). Modelling of Concurrent Systems in Hardware Languages. In: Prototyping of Concurrent Control Systems Implemented in FPGA Devices. Advances in Industrial Control. Springer, Cham. https://doi.org/10.1007/978-3-319-45811-3_8
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