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Fundamentals of Electromigration in Interconnects of 3D Packaging

  • Pilin LiuEmail author
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 57)

Abstract

Micro bumps, through Si vias (TSV), and redistribution layers (RDL) or back-end-of-line (BEOL) layers that connected to the TSV are unique interconnects connecting the stacked Si dies in 3D packaging. Electromigration (EM) failure has been a concern for these interconnects due to high current density and joule heating. In this chapter, the key EM failure modes in these interconnects are summarized. By leveraging the EM learning from flip chip first-level interconnect solder joints and damascene Cu interconnects, failure mechanisms and factors that modulate the EM of micro bumps, TSV, and its connected Cu layers are also summarized. The impact of the unique micro bump dimensions and structures on EM will be highlighted.

Keywords

Solder Joint Solder Alloy Back Stress Flip Chip Solder Joint Electron Wind Force 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgment

The editors would like to thank Kwang-Lung Lin from National Cheng Kung University in Taiwan for his critical review of this chapter.

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.Intel CorporationChandlerUSA

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