Materials and Processing of TSV

  • Praveen Kumar
  • Indranath DuttaEmail author
  • Zhiheng Huang
  • Paul Conway
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 57)


This chapter introduces the critical steps involved in fabricating through-silicon vias (TSVs) and associated materials. The fabrication steps for TSVs begin with etching of high aspect ratio trenches in Si, followed by placement of dielectric, barrier and seed layers, TSV filling and polishing, and then assembly with other components of a device. In addition, planarization, die-thinning and flow processes to fabricate TSV-enabled 3-D architectured microelectronic package are described. Challenges associated with processing of TSVs as well as methods for overcoming them are highlighted and discussed.


Barrier Layer Dielectric Layer High Aspect Ratio Atomic Layer Deposition Metal Filler 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The editors would like to thank Purushotham Kaushik Muthur Srinath and Shengquan E Ou from Intel Corporation for their critical review of this chapter. The authors (PK and ID) acknowledge financial support for some of the reported work by the National Science Foundation (DMR-0513874 and DMR-1309843), Cisco Research Council and the Semiconductor Research Corporation. PK would also like to acknowledge financial support from Department of Science and Technology, India (grant number DSTO 1164). The contributions of, and collaborations with several colleagues (Dr. Lutz Meinshausen, formerly of Washington State University, and currently at Global Foundries, Dresden, Germany; Dr. Tae-Kyu Lee, formerly of Cisco Systems, and currently at Portland State University; Dr. Ravi Mahajan of Intel Corporation; Dr. Vijay Sarihan of Freescale Semiconductor, and Professor Muhannad Bakir of Georgia Tech) are gratefully acknowledged. The assistance of current and former colleagues (Dr. Hanry Yang of Washington State University, and Dr. Zhe Huang, formerly of Washington State University, and currently at Seagate Technologies) with the literature survey is also gratefully acknowledged. The author (ZH) acknowledges financial support for his research by the Pearl River Science and Technology Nova Program of Guangzhou under grant no. 2012J2200074, the National Natural Science Foundation of China (NSFC) under grant no. 51004118 and Guangdong Natural Science Foundation under grant no. 2015A030312011.


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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Praveen Kumar
    • 1
  • Indranath Dutta
    • 2
    Email author
  • Zhiheng Huang
    • 3
  • Paul Conway
    • 4
  1. 1.Department of Materials EngineeringIndian Institute of ScienceBangaloreIndia
  2. 2.School of Mechanical and Materials EngineeringWashington State UniversityPullmanUSA
  3. 3.School of Materials Science and EngineeringSun Yat-sen UniversityGuangzhouChina
  4. 4.The Wolfson School of Mechanical, Electrical and Manufacturing EngineeringLoughborough UniversityLoughboroughUK

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