3D Packaging Architectures and Assembly Process Design

  • Ravi MahajanEmail author
  • Bob Sankman
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 57)


In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.


Heterogeneous integration TSV 3D stacking Assembly Packaging Micro-bumping 



Two dimensional


Three dimensional


Back end of line




Chemical mechanical polishing






Electro-chemical deposition


Deleted in chapter


Embedded multi-die interconnect bridge


Front end of line


Intellectual property


Known good die


Keep out zone


Multi chip module


Multi chip package


Middle end of line


Multi package module


Plasma enhanced chemical vapor deposition


Plasma vapor deposition




Side by side


System in package


System on chip


Thermal design power


Thermal interface material


Through silicon via







The authors would like to acknowledge Prismark Partners LLC, TechSearch International Inc, Shinko Electric Industries Co., Ltd, Amkor Technology®, ASE Group, SK Hynix, for their generous permission to use their pictures. Thanks are also due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Upendra Sheth (Intel Corporation) for his help in compiling information on different MCP technologies, Dr. Arnab Choudhury (Intel Corporation) for help with thermal analysis and Prasad Ramanathan (Intel Corporation) for help with images. Guidance from Chris Nelson (Intel Corporation) on test processes is also gratefully acknowledged. Finally, thanks are due to Dheeraj Reddy (Intel Corporation) for a thorough review of this chapter.


  1. 1.
    G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114 (1965)Google Scholar
  2. 2.
    R. Thakur, 50 years of Moore’s law. Solid State Technology 58(4), 41 (2015)Google Scholar
  3. 3.
  4. 4.
    R.R. Tummala, System on Package: Miniaturization of the Entire System (McGraw-Hill, New York, 2008)Google Scholar
  5. 5.
  6. 6.
    W.R. Davis, J. Wilson, J. Xu, L. Luo, H. Hua, A. Sule, C.A. Mineo, M.B. Steer, P.D. Franzon, Demystifying 3D ICs: The pros and cons of going vertical. IEEE Des. Test Comput. 22(6), 498–510 (2005)CrossRefGoogle Scholar
  7. 7.
  8. 8.
    C.C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T. Wang, S.-P. Jeng, D.C.H. Yu, High performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration, in IEEE IEDM, 2012, pp. 323–326Google Scholar
  9. 9.
    R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, D. Mallik, Embedded multi-die interconnect bridge (EMIB)—a high density, high bandwidth packaging interconnect. Paper presented at the 66th electronic components and technology conference, Las Vegas, NV, pp. 557–565, June 2016Google Scholar
  10. 10.
  11. 11.
    J.D. Meindl, Interconnect opportunities for gigascale integration, in IEEE Micro 2003, pp. 28–35Google Scholar
  12. 12.
    J.D. Meindl, Beyond Moore’s law: The interconnect era, in Computing in Science and Engineer, 2003 IEEE, 2003, pp. 20–24Google Scholar
  13. 13.
    R.S. Patti, Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94(6), 1214–1224 (2006)CrossRefGoogle Scholar
  14. 14.
    F. Mukta, S.S. Iyer, 3D integraion review. Sci. China Inf. Sci. 54(5), 1012–1025 (2011)CrossRefGoogle Scholar
  15. 15.
    G.G. Vakanas, O. Minho, B. Dimcic, K. Vanstreels, B. Vandecasteele, I. De Preter, J. Derakhshandeh, K. Rebibis, M. Kajihara, I. De Wolf, Formation, processing and characterization of Co-Sn intermetallic compounds for potential integration in 3D interconnects. Microelectron. Eng. 140, 72–80 (2015)CrossRefGoogle Scholar
  16. 16.
    A. Eitan, K.-Y. Hung, Thermo-compression bonding for fine-pitch copper-pillar flip-chip interconnect—tool features as enablers of unique technology, in Proceedings IEEE 65th Electronic Components and Technology Conference (ECTC), pp. 460–464, May 2015Google Scholar
  17. 17.
    A. Klumpp, R. Merkel, P. Ramm, J. Weber, R. Weiland, Vertical system integration by using inter-chip vias and solid-liquid interdiffusion bonding. Jpn. J. Appl. Phy. 43(7A), L829–L830 (2004)CrossRefGoogle Scholar
  18. 18.
    P. Batra, S. Skordas, D. LaTulipe, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He, D.W. Gamage, J. Golz, W. Lin, T. Vo, D. Priyadarshini, A. Hubbard, K. Cauffman, B. Peethala, J. Barth, T. Kirihata, T. Graves-Abe, N. Robson, S. Iyer, Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology. J. Low Power Electron. Appl. 4, 77–89 (2014). doi: 10.3390/jlpea4020077 CrossRefGoogle Scholar
  19. 19.
    K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, M. Bonkohara, Ultra-high-density Interconnection technology of three-dimensional packaging. Microelectron. Reliab. 43, 1267–1279 (2003)CrossRefGoogle Scholar
  20. 20.
    C.S. Tan, G.Y. Chong, High throughput Cu-Cu bonding by non-thermo-compression method. Paper presented at the 63rd electronic components and technology conference, Las Vegas, NV, pp. 1158–1164, May 2013Google Scholar
  21. 21.
    P. Guegen, C. Ventosa, L. Di Cioccio, H. Moriceau, F. Grossi, M. Rivoire, P. Leduc, L. Clavelier, Physics of direct bonding: applications to 3D heterogeneous or monolithic integration. Microelectron. Eng. 87, 477–484 (2010)CrossRefGoogle Scholar
  22. 22.
  23. 23.
  24. 24.
    S. Lhostis, A. Farcy, E. Deloffre, F. Lorut, S. Mermoz, Y. Henrion, L. Bethier, F. Bailly, D. Scevola, F. Gyuader, F. Gigon, C. Besset, S. Pellssier, L. Gay, N. Hetellier, M. Arnoux, A.-L. Le Berrigo, S. Moreau, V. Balan, F. Fournel, A. Jouce, S. Cheramy, B. Rebhan, G. Maier, L. Chitu, Reliable 300mm wafer level hybrid bonding for 3D stacked CMOS image sensors. Paper presented at the 66th electronic components and technology conference, Las Vegas, NV, pp. 869–876, June 2016Google Scholar
  25. 25.
    V.C. Venezia, C. Shih, W.Z. Yang, B. Zhang, H. Rhodes, Stack chip technology: a new direction for CMOS imagers. Paper presented at the IISW conference 2015Google Scholar
  26. 26.
    R. Fontaine, The state-of-the-art of mainstream CMOS image sensors. Paper presented at the IISW conference 2015Google Scholar
  27. 27.
    B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G.H. Loh, D. McCauley, P. Morrow, D.W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, Die stacking (3D) microarchitecture. Paper presented at the 39th annual IEEE/ACM international symposium on microarchitecture (MICRO’06) 2006Google Scholar
  28. 28.
    J.M. Stern, V.H. Ozguz, 3D system architectures, in Intelligent Integrated Microsystems, ed. by R.A. Athale, J.C. Wolper, Proc. of SPIE 6232 6232K (2006). doi: 10.1117/12.667381
  29. 29.
    P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, J.F. McDonald, Predicting the performance of a 3D processor-memory chip stack. IEEE Des. Test Comput. 22, 540–547 (2005)CrossRefGoogle Scholar
  30. 30.
    P. Franzon, E. Rotenberg, J. Tuck, W.R. Davis, H. Zhou, J. Schabel, Z. Zhang, J.B. Dwiel, E. Forbes, J. Huh, S. Lipa, Computing in 3D. Presented at the 2015 custom integrated circuits conference (CICC), 2015 IEEE, pp. 1–6, 28–30 Sept. 2015Google Scholar
  31. 31.
    K. Chandrashekar, W. Weis, B. Akesson, N. When, K. Goossens, System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. Presented at the 2013 DATE conference, pp. 236–241Google Scholar
  32. 32.
    M.A. Karim, P.D. Franzon, A. Kumar, Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects, in ECTC 2013, pp. 860–866Google Scholar
  33. 33.
    M.H. Hajkazemi, M.K. Tavana, H. Homayoun, Wide I/O or LPDDR? exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs. Paper presented at the 33rd IEEE international conference on computer design, 2015, pp. 70–77Google Scholar
  34. 34.
    M. Saeidi, K. Samadi, A. Mittal, R. Mittal, Thermal implications of mobile 3D-ICs. Presented at the 2014 3D systems integration conference (3DIC) in Kinsdale. doi: 10.1109/3DIC.2014.7152160, pp. 1–7
  35. 35.
    M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, H. Itani, Future system-on-silicon LSI chips. IEEE Micro. 18(4), 17–22 (1998)CrossRefGoogle Scholar
  36. 36.
    A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas, S. Domae, D. Perry, M. Choi, A. Redolifi, C. Okoro, Y. Yang, J. Van Olmen, S. Thangaraju, D. Sabuncuoglu Tezcan, P. Soussan, J.H. Cho, A. Yakovlev, P. Marchal, Y. Travaly, E. Beyne, S. Biesemans, B. Swinnen, Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-K/metal gate CMOS performance, in IEDM, pp. 2.2.1–2.2.4, 2010Google Scholar
  37. 37.
    W. Guo, G. Van der Plas, A. Ivankovic, V. Cherman, G. Eneman, B. De Wachter, M. Togo, A. Redolfi, S. Kubicek, Y. Civale, T. Chiarella, B. Vandevelde, K. Croes, I. De Wolf, I. Debusschere, A. Mercha, A. Thean, G. Beyer, B. Swinnen, E. Beyne. Impact of through silicon via induced mechanical stress on fully depleted bulk finFET technology, in IEDM, pp. 18.4.1–18.4.4, 2012Google Scholar
  38. 38.
    T. Kauerauf, A. Branka, K. Croes, A. Redolfi, Y. Civale, C. Torregiani, G. Groeseneken, E. Beyne, Effect of TSV presence on FEOL yield and reliability, pp. 5C.6.1–5C.6.4, 2013Google Scholar
  39. 39.
    M. Tanaka, M. Sekine, I. Sakai, Y. Kusuda, T. Nonaka, O. Ysuji, K. Kondo, TSV processes, in Three dimensional integration of semiconductors, pp. 43–96 (2015).
  40. 40.
    T.M. Bauer, S.L. Shinde, J.E. Massad, D.L. Hetherington, Front end of line integration of high density, electrically isolated, metallized through silicon vias, in Proceedings of the 58th Electronic Components and Technology Conference (ECTC), pp. 1165–1169, May 2009Google Scholar
  41. 41.
    M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, Fabrication of 3D packaging TSV using DRIE, design, test, integration and packaging of MEMS/MOEMS, 2008, in MEMS/MOEMS 2008. Symposium on, 2008, pp. 109–114. doi: 10.1109/DTIP.2008.4752963
  42. 42.
    G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J.F. Lugand, R. Anciant, N. Sillon, Through silicon via technology using tungsten metallization, in 2011 I.E. International Conference on IC Design & Technology, 2011, pp. 1–4. doi: 10.1109/ICICDT.2011.5783204
  43. 43.
    R. Agarwal, D. Hiner, S. Kannan, K. Lee, D. Kim, J. Paek, S. Kang, Y. Song, S. Dej, D. Smith, S. Thangaraju, J. Paul, TSV integration on 20nm logic: 3D Assembly and reliability results, in Proceedings of the 64th Electronic Components and Technology Conference (ECTC), pp. 590–595, May 2014Google Scholar
  44. 44.
    D.J. Na, K.O. Aung, W.K. Choi, T. Kida, T. Ochiai, T. Hashimoto, M. Kimura, K. Kata, S.W. Yoon, A.C.B. Yong, TSV MEOL (Mid End of Line) and packaging technology of mobile 3D-IC stacking, in Proceedings of the 64th Electronic Components and Technology Conference (ECTC), pp. 596–600, May 2014Google Scholar
  45. 45.
    N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Z. Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke, Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation, in 2012 I.E. 62nd Electronic Components and Technology Conference, pp. 787–793. doi: 10.1109/ECTC.2012.6248922
  46. 46.
    E. Beyne, Reliable via-middle copper through-silicon via technology for 3-D integration. IEEE Trans. Compon. Packag. Manuf. Technol. 6(7), 983–992 (2016). doi: 10.1109/TCPMT.2015.2495166 CrossRefGoogle Scholar
  47. 47.
    S.W. Yoon, D.J. Na, K.T. Kang, W.K. Choi, C.B. Yong, Y.C. Kim, P.C. Marimuthu, TSV MEOL (Mid-End-Of-Line) and its assembly/packaging technology for 3D/2.5D solutions, in ICEP-IAAC 2012 Proceedings, pp. 1–5Google Scholar
  48. 48.
    K.-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J.-C. Bea, T. Fukushima, T. Tananka, M. Koyanagi, A resilient 3D stacked multicore processor fabricated using die-level 3D integration and backside TSV technologies. in Proceedings of the 64th Electronic Components and Technology Conference (ECTC), pp. 304–308, May 2014Google Scholar
  49. 49.
    M.-J. Tsai, Overview of ITRI’s TSV technology, in 7th Annual SEMATECH Symposium Japan, June 2011,
  50. 50.
    H. Ikeda, Heterogeneous 3D stacking technology developments in ASET, in CPMT Symposium Japan, 2012 2nd IEEE, 2012, pp. 1–4. doi: 10.1109/ICSJ.2012.6523453
  51. 51.
    H.B. Chang, H.Y. Chen, P.C. Kuo, C.H. Chien, E.B. Liao, T.C. Lin, T.S. Wei, Y.C. Lin, Y.H. Chen, K.F. Yang, H.A. Teng, W.C. Tsai, Y.C. Tseng, S.Y. Chen, C.C. Hsieh, M.F. Chen, Y.H. Liu, T.J. Wu, S.Y. Hou, W.C. Chiou, S.P. Jeng, C.H. Yu, High-aspect ratio through silicon via (TSV) technology, in 2012 Symposium on VLSI Technology Digest of Technical Papers, pp. 173–174Google Scholar
  52. 52.
    P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam, 3D interconnect through aligned wafer level bonding, in Proceedings of the 52nd Electronic Components and Technology Conference (ECTC), pp. 1439–1443, May 2002Google Scholar
  53. 53.
    T. Ohba, Wafer level three-dimensional integration (#DI) using bumpless TSV interconnects for tera-scale generation, in 2013 IEEE, 2013, pp. 1–4Google Scholar
  54. 54.
    Q. Chen, D. Zhang, Z. Wang, L. Liu, J.J.-Q. Lu, Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding, in Proceedings of the 61st Electronic Components and Technology Conference (ECTC), pp. 1–6, May 2011Google Scholar
  55. 55.
    W.K. Choi, C.S. Premchandran, L. Xie, S.C. Ong, J.H. He, G.J. Yap, A. Yu, A novel die to wafer (D2W) collective bonding method for MEMs and electronics a heterogeneous 3D integration, in Proceedings of the 60th Electronic Components and Technology Conference (ECTC), pp. 829–833, May 2010Google Scholar
  56. 56.
    K. Sakuma, P.S. Andy, C.K. Tsang, S.L. Wright, B. Dang, C.S. Patel, B.C. Webb, J. Maria, E.J. Sprogis, S.K. Kang, R.J. Polastre, R.R. Horton, J.U. Knockerbocker, 3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res. Dev. 52(6), 611–622 (2008)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.High Density Interconnect Pathfinding, Assembly Technology, Intel CorporationChandlerUSA

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