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3D Packaging Architectures and Assembly Process Design

  • Ravi MahajanEmail author
  • Bob Sankman
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 57)

Abstract

In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

Keywords

Heterogeneous integration TSV 3D stacking Assembly Packaging Micro-bumping 

Acronyms

2D

Two dimensional

3D

Three dimensional

BEOL

Back end of line

BI

Burn-In

CMP

Chemical mechanical polishing

D2D

Die-to-die

D2W

Die-to-wafer

ECD

Electro-chemical deposition

ECG

Deleted in chapter

EMIB

Embedded multi-die interconnect bridge

FEOL

Front end of line

IP

Intellectual property

KGD

Known good die

KOZ

Keep out zone

MCM

Multi chip module

MCP

Multi chip package

MEOL

Middle end of line

MPM

Multi package module

PECVD

Plasma enhanced chemical vapor deposition

PVD

Plasma vapor deposition

Rx

Receiver

SBS

Side by side

SIP

System in package

SOC

System on chip

TDP

Thermal design power

TIM

Thermal interface material

TSV

Through silicon via

Tx

Transmitter

W2W

Wafer-to-wafer

Notes

Acknowledgments

The authors would like to acknowledge Prismark Partners LLC, TechSearch International Inc, Shinko Electric Industries Co., Ltd, Amkor Technology®, ASE Group, SK Hynix, for their generous permission to use their pictures. Thanks are also due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Upendra Sheth (Intel Corporation) for his help in compiling information on different MCP technologies, Dr. Arnab Choudhury (Intel Corporation) for help with thermal analysis and Prasad Ramanathan (Intel Corporation) for help with images. Guidance from Chris Nelson (Intel Corporation) on test processes is also gratefully acknowledged. Finally, thanks are due to Dheeraj Reddy (Intel Corporation) for a thorough review of this chapter.

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.High Density Interconnect Pathfinding, Assembly Technology, Intel CorporationChandlerUSA

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