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Processing and Reliability of Solder Interconnections in Stacked Packaging

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3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 57))

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Abstract

Three-dimensional (3D) packaging, whether stacked die or stacked packages, has been a critical enabler in the further miniaturization and increased functionality of hand-held, consumer electronics. Similarly, reducing the size, weight, and power (SWaP) requirements of high-reliability electronics is an omnipresent goal of the military, space, and satellite communities. Yet, there remains to be an information gap with respect to the long-term performance of 3D packaging in high-reliability electronics that has not been sufficiently addressed by the original equipment manufacturers (OEMs) of consumer products. This chapter helps to fill this gap by highlighting the materials, processes, and growing reliability database of the stacked-package variant within 3D technology. Emphasis is placed on the solder interconnections used to assemble individual packages together as well as the second-level interconnections made between the stacked package and the printed circuit board (PCB). After a brief description of the seemingly divergent reliability requirements between consumer and high-reliability electronics, the discussion turns to the materials and soldering processes used in the assembly of the two common stacked packaging formats—package-on-package (PoP) and package-on-package-on-package (PoPoP). The next section examines solder joint reliability, including service conditions versus accelerated aging tests as well as the impacts of encapsulants and underfills on the long-term performance of PoP and PoPoP interconnections. Particular attention is given to computational modeling that will most certainly be a required toolset for predicting the solder joint reliability of these complex structures. Concluding remarks address the future trends of stacked packages and their potential to significantly enhance the functionality of high-reliability systems while also reducing SWaP.

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Acknowledgments

The author wishes to thank all of the individuals who have contributed to the projects that have allowed for the construction of this chapter: Jerry Rejent and Mark Grazier who performed all of the experimental work, the folks responsible for the microanalysis: Alice Kilgo, Amy Allen, Bonnie McKenzie, and Richard Grant; as well as the continued support by M. Rightly, R. Periasamy, and Dan Baker. Also, a “thank you” goes to Brian Wroblewski for his careful review of the manuscript. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract No. DE-AC04-94AL85000.

The editors would like to thank Luhua Xu from Intel Corporation for his critical review of this Chapter.

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Authors and Affiliations

  1. Sandia National Laboratories, Albuquerque, NM, USA

    Paul Vianco

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  1. Paul Vianco
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Correspondence to Paul Vianco .

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Editors and Affiliations

  1. Intel Corporation, Chandler, Arizona, USA

    Yan Li

  2. Intel Corporation, Chandler, Arizona, USA

    Deepak Goyal

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Vianco, P. (2017). Processing and Reliability of Solder Interconnections in Stacked Packaging. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 57. Springer, Cham. https://doi.org/10.1007/978-3-319-44586-1_13

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  • DOI: https://doi.org/10.1007/978-3-319-44586-1_13

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-44584-7

  • Online ISBN: 978-3-319-44586-1

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